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DS30010118D-page 125

PIC24FJ256GA705 FAMILY

11.0 I/O PORTS

All of the device pins (except VDD, VSS, MCLR and

OSCI/CLKI) are shared between the peripherals and the

Parallel I/O (PIO) ports. All I/O input ports feature

Schmitt Trigger (ST) inputs for improved noise immunity.

11.1

Parallel I/O (PIO) Ports

A Parallel I/O port that shares a pin with a peripheral is,

in general, subservient to the peripheral. The periph-

eral’s output buffer data and control signals are

provided to a pair of multiplexers. The multiplexers

select whether the peripheral or the associated port

has ownership of the output data and control signals of

the I/O pin. The logic also prevents “loop through”, in

which a port’s digital output can drive the input of a

peripheral that shares the same pin. Figure 11-1 shows

how ports are shared with other peripherals and the

associated I/O pin to which they are connected.

When a peripheral is enabled and the peripheral is

actively driving an associated pin, the use of the pin as a

general purpose output pin is disabled. The I/O pin may

be read, but the output driver for the parallel port bit will be

disabled. If a peripheral is enabled, but the peripheral is

not actively driving a pin, that pin may be driven by a port.

All port pins have three registers directly associated

with their operation as digital I/Os and one register

associated with their operation as analog inputs. The

Data Direction register (TRISx) determines whether the

pin is an input or an output. If the data direction bit is a

‘1’, then the pin is an input. All port pins are defined as

inputs after a Reset. Reads from the Output Latch

the latch. Reads from the PORTx register, read the port

pins; writes to the port pins, write the latch.

Any bit and its associated data and control registers that

are not valid for a particular device will be disabled. That

means the corresponding LATx and TRISx registers,

and the port pin, will read as zeros. Table 11-3 through

Table 11-5 show ANSELx bits and ports availability for

device variants. When a pin is shared with another

peripheral or function that is defined as an input only, it

is regarded as a dedicated port because there is no

other competing source of inputs.

FIGURE 11-1:

BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE

Note:

This data sheet summarizes the features of

this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. For more information, refer to

the “dsPIC33/PIC24 Family Reference

Manual”, “I/O Ports with Peripheral

Pin Select (PPS)” (DS39711), which is

available from the Microchip website

(www.microchip.com). The information in

this data sheet supersedes the information

in the FRM.

WR LATx +

TRIS Latch

I/O Pin

WR PORTx

Data Bus

Data Latch

Read PORTx

Read TRISx

WR TRISx

Peripheral Output Data

Output Enable

Peripheral Input Data

I/O

Peripheral Module

Peripheral Output Enable

PIO Module

Output Multiplexers

Output Data

Input Data

Peripheral Module Enable

Read LATx

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