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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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DVR 数据表(PDF) 163 Page - Microchip Technology |
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DVR 数据表(HTML) 163 Page - Microchip Technology |
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163 / 416 page  2016-2018 Microchip Technology Inc. DS30010118D-page 163 PIC24FJ256GA705 FAMILY FIGURE 13-2: TIMER2 (16-BIT SYNCHRONOUS) BLOCK DIAGRAM FIGURE 13-3: TIMER3 (16-BIT ASYNCHRONOUS) BLOCK DIAGRAM TON TCKPS<1:0> Prescaler 1, 8, 64, 256 2 T2CK Set T2IF Equal Reset Q QD CK TGATE 1 0 Sync Note 1: The timer clock input must be assigned to an available RPn/RPIn pin before use. See Section 11.5 “Peripheral Pin Select (PPS)” for more information. TMR2 TCY TCS(1) TGATE(1) SOSC Input LPRC Input TECS<1:0> TxCK Gate Sync Comparator PR2 TON TCKPS<1:0> 2 PR3 Set T3IF Equal Comparator TMR3 Reset Q QD CK TGATE 1 0 A/D Event Trigger(2) Prescaler 1, 8, 64, 256 Note 1: The timer clock input must be assigned to an available RPn/RPIn pin before use. See Section 11.5 “Peripheral Pin Select (PPS)” for more information. 2: The A/D event trigger is available only on Timer3. T3CK TCY TCS(1) TGATE(1) SOSC Input LPRC Input TECS<1:0> TxCK Gate Sync |
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