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DS30010118D-page 173

PIC24FJ256GA705 FAMILY

15.0 OUTPUT COMPARE WITH

DEDICATED TIMERS

All devices in the PIC24FJ256GA705 family feature

three independent output compare modules. Each of

these modules offers a wide range of configuration and

operating options for generating pulse trains on internal

device events, and can produce Pulse-Width Modulated

(PWM) waveforms for driving power applications.

Key features of the output compare module include:

• Hardware-Configurable for 32-Bit Operation in

All modes by Cascading Two Adjacent modules

• Synchronous and Trigger modes of Output

Compare Operation with up to 31 User-Selectable

Sync/Trigger Sources Available

• Two Separate Period registers (a main register,

OCxR, and a secondary register, OCxRS) for

Greater Flexibility in Generating Pulses of

Varying Widths

• Configurable for Single Pulse or Continuous

Pulse Generation on an Output Event, or

Continuous PWM Waveform Generation

• Up to Six Clock Sources Available for Each module,

Driving a Separate Internal 16-Bit Counter

15.1

General Operating Modes

15.1.1

SYNCHRONOUS AND TRIGGER

MODES

When the output compare module operates in a Free-

Running mode, the internal 16-bit counter, OCxTMR,

runs counts up continuously, wrapping around from

0xFFFF to 0x0000 on each overflow. Its period is

synchronized to the selected external clock source.

Compare or PWM events are generated each time a

match between the internal counter and one of the

Period registers occurs.

In Synchronous mode, the module begins performing

its compare or PWM operation as soon as its selected

clock source is enabled. Whenever an event occurs on

the selected Sync source, the module’s internal

counter is reset. In Trigger mode, the module waits for

a Sync event from another internal module to occur

before allowing the counter to run.

Free-Running mode is selected by default or any time

that the SYNCSEL<4:0> bits (OCxCON2<4:0>) are set

to ‘00000’. Synchronous or Trigger modes are selected

any time the SYNCSELx bits are set to any value except

‘00000’. The OCTRIG bit (OCxCON2<7>) selects either

Synchronous or Trigger mode; setting the bit selects

Trigger mode operation. In both modes, the SYNCSELx

bits determine the Sync/Trigger source.

15.1.2

CASCADED (32-BIT) MODE

By default, each module operates independently with

its own set of 16-Bit Timer and Duty Cycle registers. To

increase resolution, adjacent even and odd modules

can be configured to function as a single 32-bit module.

(For example, Modules 1 and 2 are paired, as are

Modules 3 and 4, and so on.) The odd numbered

module (OCx) provides the Least Significant 16 bits of

the 32-bit register pairs and the even numbered

module (OCy) provides the Most Significant 16 bits.

Wrap-arounds of the OCx registers cause an increment

of their corresponding OCy registers.

Cascaded operation is configured in hardware by set-

ting the OC32 bit (OCxCON2<8>) for both modules.

For more details on cascading, refer to the “dsPIC33/

PIC24 Family Reference Manual”, “Output Compare

with Dedicated Timer” (DS70005159).

Note:

This data sheet summarizes the features of

this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. For more information, refer to

the “dsPIC33/PIC24 Family Reference

Manual”,

“Output

Compare

with

Dedicated Timer” (DS70005159), which

is available from the Microchip website

(www.microchip.com). The information

in this data sheet supersedes the

information in the FRM.

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