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CS47L35 数据表(PDF) 39 Page - Cirrus Logic |
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CS47L35 数据表(HTML) 39 Page - Cirrus Logic |
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39 / 300 page  DS1085F3 39 CS47L35 4.3 Digital Core 4.2.8 DMIC Pin Configuration DMIC operation on input paths IN1 and IN2 is selected using INn_MODE, as described in Table 4-3. If DMIC is selected, the respective DMICCLKn and DMICDATn pins are configured as digital outputs and inputs, respectively. The CS47L35 provides integrated pull-down resistors on each of the DMICDATn pins. This provides a flexible capability for interfacing with other devices. The DMICDAT1 and DMICDAT2 pull-down resistors can be configured independently using the bits described in Table 4-6. Note that, if the DMICDATn DMIC input paths are disabled, the pull-down is disabled on the respective pin. 4.3 Digital Core The CS47L35 digital core provides extensive mixing and processing capabilities for multiple signal paths. The configuration is highly flexible, and virtually every conceivable input/output connection can be supported between the available processing blocks. The digital core provides parametric equalization (EQ) functions, DRC, low-/high-pass filters (LHPF), and programmable DSP capability. The DSP can support functions such as wind-noise, side-tone, or other programmable filters, also dynamic range control and compression, or virtual surround sound and other audio enhancements. 0x1B –50.5 0x4C –26.0 0x7D –1.5 0xAE 23.0 0x1C –50.0 0x4D –25.5 0x7E –1.0 0xAF 23.5 0x1D –49.5 0x4E –25.0 0x7F –0.5 0xB0 24.0 0x1E –49.0 0x4F –24.5 0x80 0.0 0xB1 24.5 0x1F –48.5 0x50 –24.0 0x81 0.5 0xB2 25.0 0x20 –48.0 0x51 –23.5 0x82 1.0 0xB3 25.5 0x21 –47.5 0x52 –23.0 0x83 1.5 0xB4 26.0 0x22 –47.0 0x53 –22.5 0x84 2.0 0xB5 26.5 0x23 –46.5 0x54 –22.0 0x85 2.5 0xB6 27.0 0x24 –46.0 0x55 –21.5 0x86 3.0 0xB7 27.5 0x25 –45.5 0x56 –21.0 0x87 3.5 0xB8 28.0 0x26 –45.0 0x57 –20.5 0x88 4.0 0xB9 28.5 0x27 –44.5 0x58 –20.0 0x89 4.5 0xBA 29.0 0x28 –44.0 0x59 –19.5 0x8A 5.0 0xBB 29.5 0x29 –43.5 0x5A –19.0 0x8B 5.5 0xBC 30.0 0x2A –43.0 0x5B –18.5 0x8C 6.0 0xBD 30.5 0x2B –42.5 0x5C –18.0 0x8D 6.5 0xBE 31.0 0x2C –42.0 0x5D –17.5 0x8E 7.0 0xBF 31.5 0x2D –41.5 0x5E –17.0 0x8F 7.5 0xC0–0xFF Reserved 0x2E –41.0 0x5F –16.5 0x90 8.0 0x2F –40.5 0x60 –16.0 0x91 8.5 0x30 –40.0 0x61 –15.5 0x92 9.0 Table 4-6. DMIC Interface Pull-Down Control Register Address Bit Label Default Description R840 (0x0348) Dig_Mic_Pad_Ctrl 1 DMICDAT2_PD 0 DMICDAT2 Pull-Down Control 0 = Disabled 1 = Enabled 0 DMICDAT1_PD 0 DMICDAT1 Pull-Down Control 0 = Disabled 1 = Enabled Table 4-5. Input Signal Path Digital Volume Range (Cont.) Input Volume Register Volume (dB) Input Volume Register Volume (dB) Input Volume Register Volume (dB) Input Volume Register Volume (dB) |
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