CS47L35 datasheet(74/300 Pages) CIRRUS

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DS1085F3

CS47L35

4.3 Digital Core

4.3.14 Isochronous Sample-Rate Converter (ISRC)

The CS47L35 supports multiple signal paths through the digital core. The ISRCs provide sample-rate conversion between

synchronized sample rates on the SYSCLK clock domain.

There are two ISRCs on the CS47L35. Each ISRC provides four signal paths between two different sample rates, as

shown in Fig. 4-27. The sample rates associated with each ISRC can each be set equal to SAMPLE_RATE_1, SAMPLE_

RATE_2, or SAMPLE_RATE_3. See Section 4.16 for details of the sample-rate control registers.

Each ISRC supports sample rates in the range 8–192 kHz. The higher of the sample rates associated with each ISRC

must be an integer multiple of the lower sample rate; all possible integer ratios are supported (i.e., up to 24).

Each ISRC converts between a sample rate selected by ISRCn_FSL and a sample rate selected by ISRCn_FSH, (where

identifies the applicable ISRC 1 or 2). Note that, in each case, the higher of the two sample rates must be selected by

ISRCn_FSH.

The ISRCn_FSL and ISRCn_FSH fields must not be changed if any of the respective x_SRCn fields is nonzero. The

associated x_SRCn fields must be cleared before writing new values to ISRCn_FSL or ISRCn_FSH. A minimum delay of

125

s must be allowed between clearing the x_SRCn fields and writing to the associated ISRCn_FSL or ISRCn_FSH

fields. See Table 4-22 for details.

The ISRC signal paths are enabled using the ISRCn_INTm_ENA and ISRCn_DECm_ENA bits, as follows:

•The ISRCn interpolation paths (increasing sample rate) are enabled by setting the ISRCn_INTm_ENA bits, (where

identifies the applicable channel).

•The ISRCn decimation paths (decreasing sample rate) are enabled by setting the ISRCn_DECm_ENA bits.

The CS47L35 performs automatic checks to confirm that the SYSCLK frequency is high enough to support the

commanded ISRC and digital mixing functions. If the frequency is too low, an attempt to enable an ISRC signal path fails.

Note that active signal paths are not affected under such circumstances.

The status bits in registers R1600–R2936 indicate the status of each of the digital mixers. If an underclocked error

condition occurs, these bits indicate which mixers have been enabled.

The ISRC signal paths and control registers are shown in Fig. 4-27.

R3584 (0x0E00)

FX_Ctrl1

14:11 FX_RATE[3:0]

0000

FX Sample Rate (EQ, LHPF, DRC)

0000 = SAMPLE_RATE_1

0001 = SAMPLE_RATE_2

0010 = SAMPLE_RATE_3

All other codes are reserved.

The selected sample rate is valid in the range 8–192 kHz.

All EQnMIX_SRCm, DRCnxMIX_SRCm, and LHPFnMIX_SRCm fields must be

cleared before changing FX_RATE.

R1048064 (0x0F_

FE00)

DSP1_Config_1

14:11 DSP1_RATE[3:0]

0000

DSP1 Sample Rate

0000 = SAMPLE_RATE_1

0001 = SAMPLE_RATE_2

0010 = SAMPLE_RATE_3

All other codes are reserved.

The selected sample rate is valid in the range 8–192 kHz.

All DSPnxMIX_SRCm fields must be cleared before changing DSPn_RATE.

R1572352 (0x17_

FE00)

DSP2_Config_1

14:11 DSP2_RATE[3:0]

0000

R2096640 (0x1F_

FE00)

DSP3_Config_1

14:11 DSP3_RATE[3:0]

0000

Table 4-21. Digital-Core Sample-Rate Control (Cont.)

Bit

Label

Default

Description

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