CS47L35 datasheet(68/300 Pages) CIRRUS

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DS1085F3

CS47L35

4.3 Digital Core

Note that the PWM signal generators cannot be selected as input to the digital mixers or signal-processing functions within

the CS47L35 digital core.

Figure 4-25. Digital-Core PWM Generator

The PWM1 and PWM2 mixer control fields (see Fig. 4-25) are located at register addresses R1600–R1615

(0x0640–0x064F).

The full list of digital mixer control registers (R1600–R2936) is provided in Section 6. Generic register field definitions are

provided in Table 4-7.

The x_SRCn fields select the input sources for the respective mixers. Note that the selected input sources must be

configured for the same sample rate as the mixer to which they are connected. Sample-rate conversion functions are

available to support flexible interconnectivity; see Section 4.3.14.

The PWM generators should be kept disabled (PWMn_ENA = 0) if SYSCLK is not enabled. The x_SRCn fields for all

digital core functions should be held at 0x00 if SYSCLK is not enabled. SYSCLK must be present and enabled before

selecting other values for these fields. See Section 4.16.4 for further details (including requirements for reconfiguring

SYSCLK while digital core functions are enabled).

The PWM sample rate (cycle time) is configured using PWM_RATE. See Table 4-21. Note that sample-rate conversion is

required when linking the PWM generators to any signal chain that is configured for a different sample rate.

The PWM_RATE field must not be changed if any of the associated x_SRCn fields is nonzero. The associated x_SRCn

fields must be cleared before writing a new value to PWM_RATE. A minimum delay of 125

s must be allowed between

clearing the x_SRCn fields and writing to PWM_RATE. See Table 4-21 for details.

The PWM generators are enabled by setting PWM1_ENA and PWM2_ENA, respectively, as described in Table 4-20.

Under default conditions (PWMn_OVD = 0), the duty cycle of the PWM generators is controlled by an audio signal path;

a 4-input mixer is associated with each PWM generator, as shown in Fig. 4-25.

PWM1MIX_VOL2

PWM1MIX_VOL3

PWM1MIX_VOL4

PWM1MIX_VOL1

GPIO

(GPn_FN = 0x048)

PWM1

PWM1_ENA

PWM1_OVD

PWM1_LVL

PWM2MIX_VOL2

PWM2MIX_VOL3

PWM2MIX_VOL4

PWM2MIX_VOL1

GPIO

(GPn_FN = 0x049)

PWM2

PWM2_ENA

PWM2_OVD

PWM2_LVL

PWM_RATE

PWM_CLK_SEL

When PWMn_OVD = 0, the PWM duty cycle is controlled by the respective digital audio mixer .

When PWMn_OVD = 1, the PWM duty cycle is set by PWMn _LVL.

PWM sample rate and clocking frequency are selected using PWM _RATE and PWM_CLK_SEL.

PWM1MIX_SRC1

PWM1MIX_SRC3

PWM1MIX_SRC4

PWM1MIX_SRC2

PWM2MIX_SRC1

PWM2MIX_SRC3

PWM2MIX_SRC4

PWM2MIX_SRC2

…

CS47L35 数据表(PDF) 68 Page - Cirrus Logic

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