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CS47L35 数据表(PDF) 21 Page - Cirrus Logic

部件名 CS47L35
功能描述  Smart Codec with Low-Power Audio DSP
PDF  300 Pages
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制造商  CIRRUS [Cirrus Logic]
网页  http://www.cirrus.com
标志 CIRRUS - Cirrus Logic

CS47L35 数据表(HTML) 21 Page - Cirrus Logic

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DS1085F3
CS47L35
3 Characteristics and Specifications
Table 3-19. Control Interface Timing—Two-Wire (I2C) Mode
The following timing information is valid across the full range of recommended operating conditions.
Parameter 1
1.Control interface
timing—I2C Mode
Symbol
Min
Typ
Max
Units
SCLK Frequency
—
—
—
3400
kHz
SCLK Low Pulse-Width
t1
160
—
—
ns
SCLK High Pulse-Width
t2
100
—
—
ns
Hold Time (Start Condition)
t3
160
—
—
ns
Setup Time (Start Condition)
t4
160
—
—
ns
SDA, SCLK Rise Time (10%–90%)
SCLK frequency > 1.7MHz
SCLK frequency > 1MHz
SCLK frequency
 1MHz
t6
t6
t6
—
—
—
—
—
—
80
160
2000
ns
ns
ns
SDA, SCLK Fall Time (90%–10%)
SCLK frequency > 1.7MHz
SCLK frequency > 1MHz
SCLK frequency
 1MHz
t7
t7
t7
—
—
—
—
—
—
60
160
200
ns
ns
ns
Setup Time (Stop Condition)
t8
160
—
—
ns
SDA Setup Time (data input)
t5
40
—
—
ns
SDA Hold Time (data input)
t9
0—
—
ns
SDA Valid Time (data/ACK output)
SCLK slew (90%–10%) = 20ns, CLOAD (SDA) = 15 pF
SCLK slew (90%–10%) = 60ns, CLOAD (SDA) = 100 pF
SCLK slew (90%–10%) = 160ns, CLOAD (SDA) = 400 pF
SCLK slew (90%–10%) = 200ns, CLOAD (SDA) = 550 pF
t10
t10
t10
t10
—
—
—
—
—
—
—
—
40
130
190
220
ns
ns
ns
ns
Pulse width of spikes that are suppressed
tps
0
—
25
ns
SCLK
(input)
SDA
t4
t3
START
t8
STOP
t2
t1
t7
t6
t5
t9
t10



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