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CS47L35 数据表(PDF) 37 Page - Cirrus Logic |
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CS47L35 数据表(HTML) 37 Page - Cirrus Logic |
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37 / 300 page  DS1085F3 37 CS47L35 4.2 Input Signal Path Whenever the gain or mute setting is changed, the signal path gain is ramped up or down to the new settings at a programmable rate. For increasing gain (or unmute), the rate is controlled by IN_VI_RAMP. For decreasing gain (or mute), the rate is controlled by IN_VD_RAMP. Note: The IN_VI_RAMP and IN_VD_RAMP fields should not be changed while a volume ramp is in progress. The IN_VU bits control the loading of the input signal path digital volume and mute controls. When IN_VU is cleared, the digital volume and mute settings are loaded into the respective control register, but do not change the signal path gain. The digital volume and mute settings on all of the input signal paths are updated when a 1 is written to IN_VU. This makes it possible to update the gain of multiple signal paths simultaneously. Note that, although the digital-volume controls provide 0.5-dB steps, the internal circuits provide signal gain adjustment in 0.125-dB steps. This allows a very high degree of gain control and smooth volume ramping under all operating conditions. Note: The 0 dBFS level of the IN1/IN2 digital input paths is not equal to the 0 dBFS level of the CS47L35 digital core. The maximum digital input signal level is –6 dBFS (see Table 3-7). Under 0 dB gain conditions, a –6 dBFS input signal corresponds to a 0 dBFS input to the CS47L35 digital core functions. The digital volume control registers are described in Table 4-4 and Table 4-5. Table 4-4. Input Signal Path Digital Volume Control Register Address Bit Label Default Description R777 (0x0309) Input_Volume_ Ramp 6:4 IN_VD_RAMP[2:0] 010 Input Volume Decreasing Ramp Rate (seconds/6 dB) This field should not be changed while a volume ramp is in progress. 000 = 0 ms 001 = 0.5 ms 010 = 1 ms 011 = 2 ms 100 = 4 ms 101 = 8 ms 110 = 15 ms 111 = 30 ms 2:0 IN_VI_RAMP[2:0] 010 Input Volume Increasing Ramp Rate (seconds/6 dB) This field should not be changed while a volume ramp is in progress. 000 = 0 ms 001 = 0.5 ms 010 = 1 ms 011 = 2 ms 100 = 4 ms 101 = 8 ms 110 = 15 ms 111 = 30 ms R785 (0x0311) ADC_Digital_ Volume_1L 9 IN_VU See Footnote 1 Input Signal Paths Volume and Mute Update. Writing 1 to this bit causes the Input Signal Paths Volume and Mute settings to be updated simultaneously 8 IN1L_MUTE 1 Input Path 1 (Left) Digital Mute 0 = Unmute 1 = Mute 7:0 IN1L_VOL[7:0] 0x80 Input Path 1 (Left) Digital Volume (see Table 4-5 for volume register definition). –64 dB to +31.5 dB in 0.5-dB steps 0x00 = –64dB 0x01 = –63.5dB … (0.5-dB steps) 0x80 = 0 dB … (0.5-dB steps) 0xBF = +31.5 dB 0xC0 to 0xFF = Reserved R789 (0x0315) ADC_Digital_ Volume_1R 9 IN_VU See Footnote 1 Input Signal Paths Volume and Mute Update. Writing 1 to this bit causes the Input Signal Paths Volume and Mute settings to be updated simultaneously 8 IN1R_MUTE 1 Input Path 1 (Right) Digital Mute 0 = Unmute 1 = Mute 7:0 IN1R_VOL[7:0] 0x80 Input Path 1 (Right) Digital Volume (see Table 4-5 for volume register definition). –64 dB to +31.5 dB in 0.5-dB steps 0x00 = –64dB 0x01 = –63.5dB … (0.5-dB steps) 0x80 = 0 dB … (0.5-dB steps) 0xBF = +31.5 dB 0xC0 to 0xFF = Reserved |
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