CS47L35 datasheet(82/300 Pages) CIRRUS

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DS1085F3

CS47L35

4.4 DSP Firmware Control

Note that the DSPn_CLK_SEL fields select a range of frequencies for each valid decode value. The clock frequency for

each DSP is derived as DSPCLK divided by 1, 2, 4, 8, or 16. The required division ratios, within the selected DSP clock

frequency ranges, are configured automatically for each DSP core.

The DSPn_CLK_SEL_STS fields indicate the clock frequency range for the respective DSP cores. These can be used to

confirm the clock frequency, in cases where code execution has a minimum clock frequency requirement. The DSPn_

CLK_SEL_STS field is only valid when the respective core is running code; typical usage of this field would be for the DSP

core itself to read the clock status and to take action as applicable, in particular, if the available clock does not meet the

application requirements.

Note that the DSPn_CLK_SEL_STS fields indicate a range of frequencies for each decode value. The exact clock

frequency for each DSP cannot be provided directly by the CS47L35, but can be derived using knowledge of the DSPCLK

frequency, if available.

4.4.2.3 DSP Code Execution

After the DSP firmware has been loaded, and the clocks configured, the DSP blocks are enabled by setting the DSPn_

CORE_ENA bits. When the DSP is configured and enabled, the firmware execution can be started by writing 1 to the

respective DSPn_START bit.

Alternative methods to trigger the firmware execution can also be configured using the DSPn_START_IN_SEL fields. Note

that this provides the capability to synchronously trigger multiple DSP blocks.

Using the DSPn_START_IN_SEL fields, the DSP firmware execution can be linked to the respective DMA function, the

IRQ2 status, DSPn start signals from another DSP, or to the FIFO status in one of the event loggers:

• DMA function: firmware execution commences when all enabled DSP input (WDMA) channel buffers have been

filled, and all enabled DSP output (RDMA) channel buffers have been emptied

•DSPn start signals: firmware execution commences when the respective start signal is triggered in the selected

DSP core

• IRQ2: firmware execution commences when one or more of the unmasked IRQ2 events has occurred

• Event logger status: firmware execution commences when the FIFO not-empty status is asserted within the

respective event logger

To enable firmware execution on the respective DSP block, the DSPn_CORE_ENA bit must be set. Note that the usage

of the DSPn_START bit may vary depending on the particular firmware that is being executed: in some applications (e.g.,

when an alternative trigger is selected using DSPn_START_IN_SEL), writing to the DSPn_START bit is not required.

The DSPCLK system clock must be configured and enabled before any DSP processing core is enabled. The DSP blocks

should be kept disabled (DSPn_CORE_ENA = 0) if DSPCLK is not enabled. See Section 4.16 for details of the system

clocks (including requirements for reconfiguring DSPCLK while DSP cores are enabled).

4.4.2.4 DSP Control Registers

The DSP memory, clocking, and code-execution control registers are described in Table 4-25.

The audio signal paths connecting to/from the DSP processing blocks are configured as described in Section 4.3. Note

that the DSP firmware must be loaded and enabled before audio signal paths can be enabled.

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