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CS47L35 数据表(PDF) 87 Page - Cirrus Logic

部件名 CS47L35
功能描述  Smart Codec with Low-Power Audio DSP
PDF  300 Pages
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制造商  CIRRUS [Cirrus Logic]
网页  http://www.cirrus.com
标志 CIRRUS - Cirrus Logic

CS47L35 数据表(HTML) 87 Page - Cirrus Logic

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DS1085F3
87
CS47L35
4.4 DSP Firmware Control
4.4.5
DSP Debug Support
General-purpose registers are provided for each DSP. These have no assigned function and can be used to assist in
algorithm development.
The JTAG interface provides test and debug access to the CS47L35, as described in Section 4.20. The JTAG interface
clock can be enabled independently for each DSP core using the DSPn_DBG_CLK_ENA bits. Note that, when the JTAG
interface is used to access any DSP core, the respective DSPn_CORE_ENA bit must also be set.
4.4.6
Virtual DSP Registers
The DSP control registers, described throughout Section 4.4 are implemented for each DSP core. Each control register
has a unique location within the CS47L35 register map.
An additional set of DSP control registers is also defined, which can be used in firmware to access any of the DSPs: the
virtual DSP (or DSP 0) registers are defined at address R4096 (0x1000) in the device register map. The full register map
listing is provided in Section 6.
Note that read/write access to the virtual DSP registers is only possible via firmware running on the integrated DSP cores.
When DSP firmware accesses the virtual registers, the registers are automatically mapped onto the control registers
corresponding to whichever DSP core is making the read/write access. For example, if DSP1 accesses these registers,
they are mapped onto the DSP1 control registers. If DSP2 accesses the virtual registers, they are mapped onto the DSP2
control registers.
The virtual DSP registers are designed to allow software to be transferable to any of the DSPs without modification to the
software code.
Table 4-27. DSP Interrupts
Register Address
Bit
Label
Default
Description
R5632 (0x1600)
ADSP2_IRQ0
1
DSP_IRQ2
0
DSP IRQ2. Write 1 to trigger the DSP_IRQ2_EINTn interrupt.
0
DSP_IRQ1
0
DSP IRQ1. Write 1 to trigger the DSP_IRQ1_EINTn interrupt.
R5633 (0x1601)
ADSP2_IRQ1
1
DSP_IRQ4
0
DSP IRQ4. Write 1 to trigger the DSP_IRQ4_EINTn interrupt.
0
DSP_IRQ3
0
DSP IRQ3. Write 1 to trigger the DSP_IRQ3_EINTn interrupt.
R5634 (0x1602)
ADSP2_IRQ2
1
DSP_IRQ6
0
DSP IRQ6. Write 1 to trigger the DSP_IRQ6_EINTn interrupt.
0
DSP_IRQ5
0
DSP IRQ5. Write 1 to trigger the DSP_IRQ5_EINTn interrupt.
R5635 (0x1603)
ADSP2_IRQ3
1
DSP_IRQ8
0
DSP IRQ8. Write 1 to trigger the DSP_IRQ8_EINTn interrupt.
0
DSP_IRQ7
0
DSP IRQ7. Write 1 to trigger the DSP_IRQ7_EINTn interrupt.
R5636 (0x1604)
ADSP2_IRQ4
1
DSP_IRQ10
0
DSP IRQ10. Write 1 to trigger the DSP_IRQ10_EINTn interrupt.
0
DSP_IRQ9
0
DSP IRQ9. Write 1 to trigger the DSP_IRQ9_EINTn interrupt.
R5637 (0x1605)
ADSP2_IRQ5
1
DSP_IRQ12
0
DSP IRQ12. Write 1 to trigger the DSP_IRQ12_EINTn interrupt.
0
DSP_IRQ11
0
DSP IRQ11. Write 1 to trigger the DSP_IRQ11_EINTn interrupt.
R5638 (0x1606)
ADSP2_IRQ6
1
DSP_IRQ14
0
DSP IRQ14. Write 1 to trigger the DSP_IRQ14_EINTn interrupt.
0
DSP_IRQ13
0
DSP IRQ13. Write 1 to trigger the DSP_IRQ13_EINTn interrupt.
R5639 (0x1607)
ADSP2_IRQ7
1
DSP_IRQ16
0
DSP IRQ16. Write 1 to trigger the DSP_IRQ16_EINTn interrupt.
0
DSP_IRQ15
0
DSP IRQ15. Write 1 to trigger the DSP_IRQ15_EINTn interrupt.
Table 4-28. DSP Debug Support
Register Address
Bit
Label
Default
Description
DSP1 Base Address = R1048064 (0x0F_FE00)
DSP2 Base Address = R1572352 (0x17_FE00)
DSP3 Base Address = R2096640 (0x1F_FE00)
Base address
DSPn_Config_1
3DSPn_DBG_CLK_ENA
0
DSPn Debug Clock Enable
0 = Disabled
1 = Enabled
Base address +0x40
DSPn_Scratch_1
31:16 DSPn_SCRATCH_1[15:0]
0x0000
DSPn Scratch Register 1
15:0 DSPn_SCRATCH_0[15:0]
0x0000
DSPn Scratch Register 0
Base address +0x42
DSPn_Scratch_2
31:16 DSPn_SCRATCH_3[15:0]
0x0000
DSPn Scratch Register 3
15:0 DSPn_SCRATCH_2[15:0]
0x0000
DSPn Scratch Register 2



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