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CS47L35 数据表(PDF) 90 Page - Cirrus Logic

部件名 CS47L35
功能描述  Smart Codec with Low-Power Audio DSP
PDF  300 Pages
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制造商  CIRRUS [Cirrus Logic]
网页  http://www.cirrus.com
标志 CIRRUS - Cirrus Logic

CS47L35 数据表(HTML) 90 Page - Cirrus Logic

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DS1085F3
CS47L35
4.5 DSP Peripheral Control
Fig. 4-29 shows a typical master I2C write transfer.
Figure 4-29. Master I2C Write
Fig. 4-30 shows a typical master I2C read transfer.
Figure 4-30. Master I2C Read
Fig. 4-31 shows a typical master I2C write/read transfer; the read transaction is preceded by a repeated start.
Figure 4-31. Master I2C Write and Read
4.5.1.6 Master Interface Control Registers
The MIF control registers are described in Table 4-30.
Table 4-30. Master Interface (MIF1) Control
Register Address
Bit
Label
Default
Description
R262146 (0x40002)
MIF1_I2C_CONFIG_2
10:1 MIF1_SLV_ADDR[9:0]
0x000
Address of Slave on which transactions are executed.
For 7-Bit Mode, lower 7 bits of field are used.
0
MIF1_ADDR_MODE
0
Selects the addressing mode of I2C Master
0 = 7-Bit Mode
1 = 10-Bit Mode
B1
D6
D0
B7
SDA
SCLK
Device Address
MIF1_SLV _ADDR
B0
B7
B0
R/W
B1
Write Data bits
MIF1_TX_BUFx_BYTEy
Write Data bits
MIF1_TX_BUFx_BYTEy
ACK
(Write)
ACK
ACK
START
STOP
Blue = Initiated by I2C Master
Purple = Initiated by I2C Slave
B1
B0
B7
Read Data bits
MIF1_RX_BUFx_BYTEy
ACK
R/W
B1
B0
B7
Read Data bits
MIF1_ RX_BUFx_BYTEy
ACK
STOP
ACK
D6
D0
SDA
SCLK
Device Address
MIF1_SLV _ADDR (Read)
START
(NACK)
Blue = Initiated by I2C Master
Purple = Initiated by I2C Slave
B1
D6
D0
B7
SDA
SCLK
Device Address
MIF1_SLV_ADDR
Device Address
MIF1_SLV_ADDR
B0
D6
B1
B0
R/W
D0
B7
Write Data bits
MIF1_TX_BUFx_BYTEy
Read D ata bits
MIF1_RX_BUFx_BYTEy
START
(Write) ACK
ACK
ACK
R/W
(Read)
STOP
ACK
Rpt
START



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