CS47L35 datasheet(32/300 Pages) CIRRUS

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DS1085F3

CS47L35

4.2 Input Signal Path

The analog line input configurations are shown in Fig. 4-7 and Fig. 4-8. Note that the microphone bias (MICBIAS) is not

used for line input connections.

4.2.3

DMIC Input

As many as four digital microphones can be connected to the CS47L35. DMIC operation on input paths IN1 and IN2 is

selected using INn_MODE, as described in Section 4.2.6.

In DMIC mode, two channels of audio data are multiplexed on the associated DMICDATn pin. Each stereo DMIC interface

is clocked using the respective DMICCLKn pin.

If DMIC input is enabled, the CS47L35 outputs a clock signal on the applicable DMICCLKn pins. The DMICCLKn

frequency is controlled by the respective INn_OSR field, as described in Table 4-1 and Table 4-3.

Note that, if the 384- or 768-kHz DMICCLKn frequency is selected for one or more of the DMIC input paths, the maximum

valid input path sample rate (all input paths) is affected as described in Table 4-1.

The DMICCLKn frequencies in Table 4-1 assume that the SYSCLK frequency is a multiple of 6.144 MHz (SYSCLK_

FRAC = 0). If the SYSCLK frequency is a multiple of 5.6448 MHz (SYSCLK_FRAC = 1), the DMICCLKn frequencies are

scaled accordingly.

The voltage reference for the IN1 and IN2 DMIC interfaces is selectable, using INn_DMIC_SUP; each interface may be

referenced to MICVDD or to the MICBIAS1B, MICBIAS2A, or MICBIAS2B levels. The voltage reference for each digital

input path should be set equal to the applicable power supply of the respective microphones.

A pair of digital microphones is connected as shown in Fig. 4-9. The microphones must be configured to ensure that the

left mic transmits a data bit when DMICCLK is high and the right mic transmits a data bit when DMICCLK is low. The

CS47L35 samples the DMIC data at the end of each DMICCLK phase. Each microphone must tristate its data output when

the other microphone is transmitting.

Note that the CS47L35 provides integrated pull-down resistors on the DMICDATn pins. This provides a flexible capability

for interfacing with other devices.

Figure 4-7. Single-Ended Line Input

Figure 4-8. Differential Line Input

Table 4-1. DMICCLK Frequency

Condition

DMICCLKn Frequency

Valid Sample Rates

Signal Passband

INn_OSR = 010

384 kHz

Up to 48 kHz

Up to 4 kHz

INn_OSR = 011

768 kHz

Up to 96 kHz

Up to 8 kHz

INn_OSR = 100

1.536 MHz

Up to 192 kHz

Up to 20 kHz

INn_OSR = 101

3.072 MHz

Up to 192 kHz

Up to 20 kHz

INn_OSR = 110

6.144 MHz

Up to 192 kHz

Up to 96 kHz

GND

Line

To ADC

VREF

IN1xN,

IN2xN

IN1xP,

IN2xP

PGA

–

To ADC

VREF

IN1xN,

IN2xN

IN1xP,

IN2xP

Line

PGA

–

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