ST7293 datasheet(49/69 Pages) STMICROELECTRONICS

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ST72E94 - ST72T94

1.2 PIN DESCRIPTION

DD. Power supply.

VSS. Ground.

OSCin, OSCout. Oscillator input and output pins.

These pins are to be connected to a parallel reso-

nant crystal or ceramic resonator. An external

clock source can also be input through OSCin.

RESET. The active low input signal forces the ini-

tialisation of the MCU. This event is the first priori-

ty interrupt. This pin is switched output low when

the Watchdog has released. It could be used to re-

set external peripherals.

INT/VPP. is the external interrupt signal. Software

configuration allows four triggering modes. In the

EPROM programming mode, this pin acts as the

programming voltage input V

PP.

ICAP (PC0). Input capture signal going to the TIM-

ER system. This signal, according to a mask op-

tion, can be an ICAP pin or PC0 pin. When PC0 is

defined as ICAP, the internal pull-up resistor is not

connected.

OCMP1 (PC1). Output compare signal coming

from the TIMER system. This output signal, ac-

cording to a mask option, can be an OCMP1 pin

(for output compare 1 of the timer) or PC1 pin.

When PC1 is defined as OCMP1, the internal pull-

up resistor is not connected.

PA0-PA7, PB0-PB7, PC0-PC5. These 22 lines

are standard I/O lines, programmable as either in-

put or output.

– PORT A. 8 Standard I/O lines, bit programma-

ble, accessed through DDRA and DRA Regis-

ters. According to a mask option, the outputs can

be defined as a standard push-pull output port or

as an open drain output port. According to anoth-

er mask option, a pull-up resistor can be added

on each line when it is defined as an input.

– PORT B. 8 Standard I/O lines bit programmable

accessed through DDRB and DRB Registers.

According to another mask option, a pull-up re-

sistor can be added on each line when it is de-

fined as an input.

– PORT C. 6 Standard I/O lines accessed through

DDRC and DRC Registers. According to a mask

option, these 6 lines can become 6 falling edge

sensitive interrupt lines all linked to a single inter-

rupt vector or 6 standard input ports tied to V

through an internal pull-up resistor. These nega-

tive edge sensitive interrupt lines can wake-up

the ST72E94 from WAIT or HALT mode. This

feature allows to build low power applications

when the ST72E94 can be waken-up from key-

board push.

ST7293 数据表(PDF) 49 Page - STMicroelectronics

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