ST7293 datasheet(11/69 Pages) STMICROELECTRONICS

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ST7294

CLOCK SYSTEM (Continued)

3.1.3 Ceramic Resonator

A ceramic resonator may be used in place of the

crystal in low cost applications. The circuit on Fig-

ure 8 is recommended when using a ceramic res-

onator. The table lists the recommended capaci-

tance and feedback resistance values. The manu-

facturer of the particular ceramic resonator being

considered should be consulted for specific infor-

mation.

3.1.4 External Clock

An external clock should be applied to the OSCin

input with the OSCout pin not connected, as

shown on Figure 6. The t

OXOV and tILCH specifica-

tions do not apply when using an external clock in-

put. The equivalent specification of the external

clock source should be used instead of t

OXOV or

ILCH.

Table 2. Recommended Settings for Crystal

Table 3. Recommended Settings for Ceramic

Resonator

2MHz

4MHz

Unit

RSMAX

400

812

COSCin

15-40

15-30

COSCout

15-30

15-25

Ω

Q30

103

2-4MHz

Unit

RSMAX

4.3

COSCin

COSCout

1-10

Ω

1250

3.2 MISCELLANEOUS REGISTER

Miscellaneous Register (000Ch)

—

Read/Write

Reset Value: 0001 000 (10h)

This is a miscellaneous 8-bit register, of which

only 4 bits are used for interrupt, slow mode and

Watchdog purposes.

b7, b4-b2 = Unused

b6 = INTP:

External Interrupt Positive allows se-

lection of the INT line triggering mode in conjunc-

tion with INTN. It can only be modified when the I

bit of the CC Register is set.

b5 = ININ:

External Interrupt Negative allows se-

lection the INT line triggering mode in conjunction

with INTP. It can only be modified when the I bit of

the CC Register is set.

b1 = SM:

Slow Mode. Setting this bit to 1 enables

Slow Mode, thus reducing power consumption. In

this mode, an extra divide-by-16 is added in the

clock circuitry.

b0 = WDOG:

Watchdog System. Whatever the

WATCHDOG ENABLE MODE mask option, the

watchdog counter is reset when WDOG is set to 1.

When the MCU is configured with the “program-

mable enable” option, the WDOG bit is low follow-

ing a reset. The bit must be set to enable the

watchdog system. Only a reset can clear WDOG.

INTP

INTN

WDOG

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