ST7293 datasheet(27/69 Pages) STMICROELECTRONICS

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ST7294

4.3.2.3 Input Capture

The ST7294 features an Input Capture register

and an Input Capture interrupt enable bit.The 16-

bit Input Capture Register, ICR1, is made up of

two 8-bit registers: the most significant byte regis-

ter, ICHR1, located at 014h, and the least signifi-

cant byte register (ICLR1) located at 015h. The

read-only register ICR1 is used to latch the value

of the free running counter after a defined transi-

tion is sensed by the input capture edge detector

on ICAP. This transition is software programmable

through the IEDG1 bit of the Timer Control Regis-

ter. When IEDG1 is set, a rising edge triggers the

capture; when IEDG1 is low, the capture is trig-

gered by a falling edge.

When an input capture occurs, flag ICF1 in the

Timer Status Register (TSR) is set. An interrupt is

requested if the interrupt enable bit ICIE of the

TCR is set, provided the I bit of the CCR is

cleared. Otherwise, the interrupt remains pending

until both conditions become true. The condition is

cleared by reading the TSR followed by an access

(read or write) to the LSB of ICR1.

The result stored in ICR1 is one more than the val-

ue of the free running counter on the rising edge of

the internal processor clock preceding the active

transition at pin ICAP (see Figure 19). This delay

is required for internal synchronization. Therefore,

the timing resolution of the input capture system is

1/4 internal clock cycle.

The free running counter is transferred to ICR1 on

each proper signal transition regardless of wheth-

er the Input Capture Flag ICF1 is set or cleared.

The ICR1 always contains the free running coun-

ter value which corresponds to the most recent in-

put capture.

After a read of the MSB of ICR1 (ICHR1), counter

transfer of input capture is inhibited until the LSB

of ICR1 (ICLR1) is also read. This characteristic

forces the minimum pulse period attainable to be

determined by the time to service the interrupt and

to execute the interrupt routine.

A read of ICLR1 does not inhibit the counter trans-

fer. Again, minimum pulse periods are the ones

which allow software to read the least significant

byte and perform needed operations. There is no

conflict between the read of ICR1 and the running

counter transfer since they occur on opposite edg-

es of the internal processor clock (see Figure 19).

The ICR1 is undetermined at power-on and is not

affected by an external reset. Hardware circuitry

has to provide protection from generating a wrong

input capture when changing the edge sensitivity

option of ICAP pin through the IEDG1 bit.

During the HALT mode, if at least one valid input

capture edge occurs at the ICAP pin, the input

capture detect circuitry is armed. This action does

not set any timer flags nor “wake-up” the MCU. If

the MCU is awaken by an interrupt, there is an ac-

tive input capture flag and data from the first valid

edge that occurred during the HALT mode. If the

HALT mode is exited by a reset, the input capture

detect circuitry is reset and thus, any active edge

that happened during the HALT mode is lost.

4.3.2.4 Output Compare

There are two output compare registers: Output

Compare Register 1 and 2 (OCR1 and OCR2).

They can be used for several purposes such as

controlling an output waveform or indicating when

a period of time has elapsed. OCMP1 pin is asso-

ciated with output compare 1; no pin is associated

with output compare 2.

The Output Compare Registers are unique be-

cause all bits are readable and writable and are

not affected by the timer hardware and reset. If a

compare function is not used, the two bytes of the

corresponding Output Compare Registers can be

used as storage locations.

Note that the same output compare interrupt ena-

ble bit is used for both output compares.

4.3.2.5 Output Compare Register 1

The Output Compare Register 1 (OCR1) is a 16-

bit register, which is made up of two 8-bit registers:

The most significant byte register (OCHR1) at ad-

dress 0016h and the least significant byte register

(OCLR1) at address 0017h. The content of OCR1

is compared with the content of the free running

counter once during every timer clock cycles, i.e.

once every 8, 4 or 2 internal processor clock peri-

ods according to the TIMER CLOCK mask option.

If match is found, the Output Compare Flag OCF1

of the TSR is set and the Output Level bit (OLVL1)

of the TCR is clocked to the OCMP1 pin (see out-

put compare timing diagram on Figure 19 and Fig-

ure 21).

OLVL1 is copied to the corresponding output level

latch and hence, to the OCMP1 pin regardless of

whether the Output Compare Flag (OCF1) is set

or not. The value in the OCR1 and the OLVL1 bit

should be changed after each successful compar-

ison in order to control an output waveform or es-

tablish a new elapsed timeout.

An interrupt accompanies a successful output

compare if the corresponding interrupt enable bit

OCIE of the TCR is set, provided the I-bit of the

CCR is cleared. Otherwise, the interrupt remains

pending until both conditions are true. It is cleared

by a read of TSR followed by an access to the LSB

of the OCR1.

16-BIT TIMER (Continued)

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