ST7293 datasheet(30/69 Pages) STMICROELECTRONICS

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ST7294

TIMER STATUS REGISTER

—

Read Only

Reset Value: Undefined

The Timer Status Register (TSR) is an 8-bit regis-

ter of which the five most significant bits contain

read-only status information and the three least

significant bits are not used..

Bit 7 = ICF1

Input Capture Flag 1

ICF1 is set when a proper edge has been sensed

by the input capture edge detector at pin ICAP.

The edge is selected by the IEDG1-bit in TCR.

ICF1 is cleared by a processor access to the TSR

while ICF1 is set followed by an access (read or

write) to the low byte of ICR1 (ICLR1).

Bit 6 = OCF1

Output Compare Flag 1

OCF1 is set when the content of the free running

counter matches the content of OCR1. It is

cleared by a processor access of TSR while OCF1

is set followed by an access (read or write) to the

low byte of OCR1.

Bit 5 = TOF

Timer Overflow

TOF is set by a transition of the free running coun-

ter from FFFFh to 0000h. It is cleared by a proces-

sor access to TSR while TOF is set followed by an

access (read or write) to the low byte of the coun-

ter low register. TOF is not affected by an access

to the Alternate Counter Register.

Bit 4 = Unused

Bit 3 = OCF2

Output Compare Flag 2

OCF2 is set when the content of the free running

counter matches the content of OCR2. It is

cleared by a processor access of TSR while OCF2

is set followed by an access (read or write) to the

low byte of OCR2.

Bit 2, 1, 0 = Unused.

ICF1

OCF1

TOF

0CF2

16-BIT TIMER (Continued)

4.3.3 Timer Registers

TIMER CONTROL REGISTER

—

Read/Write

Reset Value: 0000 00X0 (00h or 02h)

The TCR is an 8 bit read/write register. Its eight

bits are defined as follows:

Bit 7 = ICIE

Input Capture Interrupt Enable

If ICIE is set, a timer interrupt is enabled whenever

the ICF1 status flags of TSR are set. If the ICIE bit

is cleared, the interrupt is inhibited.

Bit 6 = OCIE

Output Compare Interrupt Enable

If OCIE is set, a timer interrupt is enabled whenev-

er the OCF1 or OCF2 status flags of TSR are set.

If the OCIE bit is cleared, the interrupt is inhibited.

Bit 5 = TOIE

Timer Overflow Interrupt Enable

If TOIE is set, a timer interrupt is enable whenever

the TOF status flag of TSR is set. If the TOIE bit is

cleared, the interrupt is inhibited.

Bit 4 = Unused

Bit 3 = FOLV1

Force Output Compare 1

When written to 1, FOLV1 forces OLVL1 to be

copied to the OCMP1 pin. FOLV1 has no effect

otherwise. It can only be reset by a system reset.

Bit 2 = Unused

Bit 1 = IEDG1

Input Edge 1

The value of the IEDG1 determines which level

transition on pin ICAP will trigger a free running

counter transfer to the ICR1. When IEDG1 is high,

a rising edge triggers the capture since when low,

a falling edge does.

Bit 0 = OLVL1

Output Level 1

The OLVL1 bit is copied to the OCMP1 pin when-

ever a successful comparison occurs at OCR1.

ICIE

OCIE

TOIE

FOLV1

IEDG1

OLVL1

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