ST7293 datasheet(12/69 Pages) STMICROELECTRONICS

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ST7294

3.3 RESETS

3.3.1 Introduction

Resets are used to provide an orderly software

start-up procedure or to exit the power-saving

modes.

Two reset modes are provided: a Power-On Reset

and an External Reset via the RESET pin.

A summary of the effects of both Reset modes on

the different sections of the MCU is given in Table

4. For further information, please refer to the rele-

vant section.

3.3.2 External Reset

The External Reset is an active-low input signal

applied to the RESET pin of the MCU.

As shown in Figure 9, the RESET signal must stay

low for a minimum of one and a half CPU clock cy-

cles. A Reset causes the Reset Vector to be

fetched at addresses 01FFEh and 01FFFh in or-

der to be loaded into the PC.

The External Reset is used by the Watchdog sys-

tem to reset the MCU. When active, the Power-On

Reset circuitry pulls down the RESET pin. In both

cases, the RESET pin may be used as an output

to reset other devices. However, the pull down cir-

cuitry features current limiting to allow the connec-

tion of any input signal, including that originating

from an RC type circuit.

An internal Schmitt trigger connected to the RE-

SET pin improves noise immunity.

3.3.3 Power-On Reset (POR)

The Power-On Reset (POR) is generated on de-

tection of a positive transition on VDD (refer to Fig-

ure 9). This causes the Reset Vector to be fetched

from addresses 01FFEh and 01FFFh, and loaded

into the PC.

Internal circuitry provides a 4096 CPU clock cycle

delay from the moment the oscillator becomes ac-

tive. At the end of the Power-On Reset, the MCU

can be maintained in the reset condition by means

of the External Reset. The RESET pin can there-

fore be used to ensure V

DD has risen to a point

where the MCU can operate properly before run-

ning the MCU program.

During the POR phase, the RESET pin is pulled

low, thus permitting the MCU to reset other devic-

es.

The Power-On Reset is strictly used for power up

conditions and should not be used to detect any

drop in the power supply voltage. There is no pro-

vision for a power-down reset.

Figure 9. Power-On Reset Timing Diagram

OSCin

CPU CLOCK

PC UNKNOWN

3FFEh

3FFFh

VR02046A

OXOV

CYC

CPU RESET

DDR

4096 t

CYC

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