TDA4VL...ALZQ1 datasheet(197/251 Pages) TI

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ASP15

ASP14

ASP13

ASP12

ASP11

ASP10

ASP9

A30 A31

B30 B31 C0

C1 C2 C3

C31

ASP13

MCASP[x]_ACLKR/X (Falling Edge Polarity)

MCASP[x]_AHCLKR/X (Rising Edge Polarity)

MCASP[x]_AFSR/X (Bit Width, 0 Bit Delay)

MCASP[x]_AFSR/X (Bit Width, 1 Bit Delay)

MCASP[x]_AFSR/X (Bit Width, 2 Bit Delay)

MCASP[x]_AFSR/X (Slot Width, 0 Bit Delay)

MCASP[x]_AFSR/X (Slot Width, 1 Bit Delay)

MCASP[x]_AFSR/X (Slot Width, 2 Bit Delay)

MCASP[x]_AXR[x] (Data Out/Transmit)

MCASP[x]_ACLKR/X (CLKRP = CLKXP = 1)

(A)

MCASP[x]_ACLKR/X (CLKRP = CLKXP = 0)

(B)

For CLKRP = CLKXP = 1, the MCASP transmitter is configured for falling edge (to shift data out) and the MCASP receiver is configured

for rising edge (to shift data in).

For CLKRP = CLKXP = 0, the MCASP transmitter is configured for rising edge (to shift data out) and the MCASP receiver is configured

for falling edge (to shift data in).

Figure 7-72. MCASP Output Timing

For more information, see Multichannel Audio Serial Port (MCASP) section in Peripherals chapter in the device

TRM.

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TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1

SPRSP62 – DECEMBER 2022

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