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TDA4VL...ALZQ1 数据表(PDF) 200 Page - Texas Instruments |
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TDA4VL...ALZQ1 数据表(HTML) 200 Page - Texas Instruments |
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200 / 251 page  SPI_CS[i] (OUT) SPI_SCLK (OUT) SPI_SCLK (OUT) SPI_D[x] (OUT) SPI_CS[i] (OUT) SPI_SCLK (OUT) SPI_SCLK (OUT) SPI_D[x] (OUT) Bit n-1 Bit n-2 Bit n-3 Bit n-4 Bit 0 Bit n-1 Bit n-2 Bit n-3 Bit 1 Bit0 PHA=0 EPOL=1 POL=0 POL=1 PHA=1 EPOL=1 POL=0 POL=1 SM8 SM9 SM6 SM3 SM1 SM2 SM1 SM8 SM9 SM3 SM1 SM2 SM1 SM6 SM7 SM6 SM2 SM3 SM2 SM3 SM6 SM6 SM6 SPRSP08_TIMING_McSPI_01 Figure 7-74. MCSPI Controller Mode Transmit Timing 7.10.5.16.2 MCSPI — Peripheral Mode Table 7-53, Table 7-54, Figure 7-75, and Figure 7-76 present timing requirements and switching characteristics for MCSPI – Peripheral Mode. Table 7-53. MCSPI Timing Requirements - Peripheral Mode NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT SS1 tc(spiclk) Cycle time, SPI_CLK 20.8 ns SS2 tw(spiclkL) Pulse duration, SPI_CLK low 0.45P(1) ns SS3 tw(spiclkH) Pulse duration, SPI_CLK high 0.45P(1) ns SS4 tsu(simoV-spiclkV) Setup time, SPI_D[x] valid before SPI_CLK active edge 5 ns SS5 th(spiclkV-simoV) Hold time, SPI_D[x] valid after SPI_CLK active edge 5 ns SS8 tsu(csV-spiclkV) Setup time, SPI_CSi valid before SPI_CLK first edge 5 ns SS9 th(spiclkV-csV) Hold time, SPI_CSi valid after SPI_CLK last edge 5 ns Table 7-54. MCSPI Switching Characteristics - Peripheral Mode NO. PARAMET ER DESCRIPTION MIN MAX UNIT SS6 td(spiclkV- somiV) Delay time, SPI_CLK active edge to SPI_D[x] transition 2 17.12 ns TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1 SPRSP62 – DECEMBER 2022 www.ti.com 200 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1 |
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