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TDA4VL...ALZQ1 数据表(PDF) 204 Page - Texas Instruments |
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TDA4VL...ALZQ1 数据表(HTML) 204 Page - Texas Instruments |
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204 / 251 page  Table 7-57. MMC0 DLL Delay Mapping for All Timing Modes (continued) REGISTER NAME MMCSD0_SS_PHY_CTRL_4_REG MMCSD0_SS_PHY_CTRL_5_REG BIT FIELD [31:24] [20] [15:12] [8] [4:0] [17:16] [10:8] [2:0] BIT FIELD NAME STRBSEL OTAPDLYENA OTAPDLYSEL ITAPDLYENA ITAPDLYSEL SELDLYTXCLK SELDLYRXCLK FRQSEL CLKBUFSEL MODE DESCRIPTION STROBE DELAY OUTPUT DELAY ENABLE OUTPUT DELAY VALUE INPUT DELAY ENABLE INPUT DELAY VALUE DLL/ DELAY CHAIN SELECT DLL REF FREQUENCY DELAY BUFFER DURATION High Speed DDR 8-bit PHY operating 1.8 V, 50 MHz 0x0 0x1 0x6 0x1 Tuning 0x0 0x4 0x7 HS200 8-bit PHY operating 1.8 V, 200 MHz 0x0 0x1 0x8 0x1 Tuning 0x0 0x0 0x7 HS400 8-bit PHY operating 1.8 V, 200 MHz 0x66 0x1 0x5 0x1 Tuning 0x0 0x0 0x7 Table 7-58 presents timing conditions for MMC0. Table 7-58. MMC0 Timing Conditions PARAMETER MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate Legacy SDR 0.14 1.44 V/ns High Speed SDR 0.3 0.90 V/ns High Speed DDR (CMD) 0.3 0.90 V/ns High Speed DDR (DAT[7:0]) 0.45 0.90 V/ns OUTPUT CONDITIONS CL Output load capacitance HS200, HS400 1 6 pF All other modes 1 12 pF PCB CONNECTIVITY REQUIREMENTS td(Trace Delay) Propagation delay of each trace All modes 134 756 ps td(Trace Mismatch Delay) Propagation delay mismatch across all traces Legacy SDR, High Speed SDR, High Speed DDR 100 ps HS200, HS400 8 ps TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1 SPRSP62 – DECEMBER 2022 www.ti.com 204 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1 |
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