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KSZ9563RNXI-TR 数据表(PDF) 159 Page - Microchip Technology |
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KSZ9563RNXI-TR 数据表(HTML) 159 Page - Microchip Technology |
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159 / 226 page  2017-2018 Microchip Technology Inc. DS00002419D-page 159 KSZ9563R 5.2.4.15 Port Queue 3 Egress Limit Control Register 5.2.5 PORT N: PORT SWITCH MIB COUNTERS REGISTERS (0xN500 - 0xN5FF) Thirty MIB counters are provided for each port. They are accessed via the following two indirect registers. MIB Counters are read-clear. Refer to Section 5.3.6, "Management Information Base (MIB) Counters" for additional details. 5.2.5.1 Port MIB Control and Status Register Address: 0xN423 Port N: 1-3 Size: 8 bits Bits Description Type Default 7 RESERVED RO 0b 6:0 Egress Data Rate Limit for Queue 3 Frames R/W 0x00 Note: The Switch MIB Control Register contains two additional bits for global control of MIB counters. Address: 0xN500 - 0xN503 Port N: 1-3 Size: 32 bits Bits Description Type Default 31 MIB Counter Overflow Indication 1 = Counter has overflowed 0 = Counter has not overflowed RO 0b 30:26 RESERVED RO 0x00 25 MIB Read Enable / Count Valid Set this bit to ‘1’ to initiate a counter read. When the counter read is complete and the count value is available in the MIB Counter Value, this bit will automatically clear to ‘0’. R/W SC 0b 24 MIB Flush and Freeze Enable Refer to the Switch MIB Control Register for the associated global MIB control bits for flushing and freezing port counters. 1 = Enable MIB counter flush and freeze function for this port 0 = Disable MIB counter flush and freeze function for this port R/W 0b 23:16 MIB Index R/W 0x00 15:4 RESERVED RO 0x000 3:0 MIB Counter Value [35:32] RO 0x0 |
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