STM32U545NET6QTR datasheet(253/283 Pages) STMICROELECTRONICS

253 / 283 page

DS14216 Rev 1

253/283

STM32U545xx

Electrical characteristics

258

Figure 53. SPI timing diagram - slave mode and CPHA = 0

tv(SO)

Data output valid

time

Slave mode, 2.7 V ≤ VDDIOX ≤ 3.6 V,

voltage range 1

-11.5

Slave mode, 1.71 V ≤ VDDIOX < 2.7 V,

voltage range 1

-11.5

13.5

or 20(4)

Slave mode, 1.71 V ≤ VDDIOX ≤ 3.6 V,

voltage range 4

-17

19.5

or 27(4)

Slave mode, 1.08 V ≤ VDDIO2 ≤ 1.32 V(5)

-21

tv(MO)

Master mode

1.5

3 or 9.5(7)

or 12.5(8)

th(SO)

Data output hold time

Slave mode, 1.71 V ≤ VDDIOX ≤ 3.6 V

Slave mode, 1.08 V ≤ VDDIO2 ≤ 1.32 V(5)

th(MO)

Master mode

0.5

1. Evaluated by characterization. Not tested in production.

2. When using PA5, PA9, PC10, PB3, PB13.

3. The maximum frequency in slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) that has to fit into SCK low

or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master

having tsu(MI) = 0 while Duty(SCK) = 50%.

4. When using PA11, PB4, PB14.

5. The SPI is mapped on port G I/Os, that is supplied by VDDIO2 specified down to 1.08V. The SPI is tested at this value.

6. tSCK = tspi_ker_ck × baudrate prescaler.

7. When using PA12.

8. When using PB15.

Table 129. SPI characteristics(1) (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

MSv41658V1

NSS input

CPHA=0

CPOL=0

CPHA=0

CPOL=1

MISO output

MOSI input

tsu(SI)

th(SI)

tw(SCKL)

tw(SCKH)

tc(SCK)

tr(SCK)

th(NSS)

tdis(SO)

tsu(NSS)

ta(SO)

tv(SO)

Next bits IN

Last bit OUT

First bit IN

First bit OUT

Next bits OUT

th(SO)

tf(SCK)

Last bit IN

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