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STM32U545NET6QTR 数据表(PDF) 256 Page - STMicroelectronics |
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STM32U545NET6QTR 数据表(HTML) 256 Page - STMicroelectronics |
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256 / 283 page  Electrical characteristics STM32U545xx 256/283 DS14216 Rev 1 Figure 56. SAI master timing diagram Figure 57. SAI slave timing digram tv(SD_A_MT) Data output valid time Master transmitter (after enable edge), 2.7 V ≤ VDD ≤ 3.6 V - 19 ns Master transmitter (after enable edge), 1.71 V ≤ VDD ≤ 3.6 V -27.5 th(SD_A_MT) Data output hold time Master transmitter (after enable edge) 8 - 1. Evaluated by characterization. Not tested in production. 2. APB clock frequency that must be at least twice SAI clock frequency. Table 130. SAI characteristics(1) (continued) Symbol Parameter Conditions Min Max Unit MS32771V1 SAI_SCK_X SAI_FS_X (output) 1/fSCK SAI_SD_X (transmit) tv(FS) Slot n SAI_SD_X (receive) th(FS) Slot n+2 tv(SD_MT) th(SD_MT) Slot n tsu(SD_MR) th(SD_MR) MS32772V1 SAI_SCK_X SAI_FS_X (input) SAI_SD_X (transmit) tsu(FS) Slot n SAI_SD_X (receive) tw(CKH_X) th(FS) Slot n+2 tv(SD_ST) th(SD_ST) Slot n tsu(SD_SR) tw(CKL_X) th(SD_SR) 1/fSCK |
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