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AD9511/PCB 数据表(PDF) 3 Page - Analog Devices |
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AD9511/PCB 数据表(HTML) 3 Page - Analog Devices |
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3 / 60 page  AD9511 Rev. A | Page 3 of 60 Single-Chip Synchronization.....................................................40 SYNCB—Hardware SYNC ....................................................40 Soft SYNC—Register 58h<2> ...............................................40 Multichip Synchronization ........................................................40 Serial Control Port ..........................................................................41 Serial Control Port Pin Descriptions........................................41 General Operation of Serial Control Port ...............................41 Framing a Communication Cycle with CSB .......................41 Communication Cycle—Instruction Plus Data..................41 Write .........................................................................................41 Read ..........................................................................................42 The Instruction Word (16 Bits).................................................42 MSB/LSB First Transfers ............................................................42 Register Map and Description.......................................................45 Summary Table............................................................................45 Register Map Description ..........................................................47 Power Supply ...................................................................................54 Power Management ....................................................................54 Applications .....................................................................................55 Using the AD9511 Outputs for ADC Clock Applications ....55 CMOS Clock Distribution.........................................................55 LVPECL Clock Distribution......................................................56 LVDS Clock Distribution...........................................................56 Power and Grounding Considerations and Power Supply Rejection.......................................................................................56 Outline Dimensions........................................................................57 Ordering Guide ...........................................................................57 REVISION HISTORY 6/05—Rev. 0 to Rev. A Changes to Features ..........................................................................1 Changes to General Description .....................................................1 Changes to Table 1 and Table 2 .......................................................5 Changes to Table 4 ............................................................................7 Changes to Table 5 ............................................................................9 Changes to Table 6 ..........................................................................14 Changes to Table 8 and Table 9 .....................................................15 Changes to Table 11 ........................................................................16 Changes to Table 13 ........................................................................20 Changes to Figure 19 to Figure 23 ................................................24 Changes to Figure 30 and Figure 31 .............................................26 Changes to Figure 32 ......................................................................27 Changes to Figure 33 ......................................................................28 Changes to VCO/VCXO Clock Input—CLK2 Section ..............29 Changes to PLL Reference Divider—P Section...........................29 Changes to A and B Counters Section .........................................30 Changes to PLL Digital Lock Detect Section ..............................31 Changes to PLL Analog Lock Detect Section..............................32 Changes to Loss of Reference Section ..........................................32 Changes to FUNCTION Pin Section ...........................................32 Changes to RESETB: 58h<6:5> = 00b (Default) Section ...........32 Changes to SYNCB: 58h<6:5> = 01b Section..............................32 Changes to CLK1 and CLK2 Clock Inputs Section ....................33 Changes to Divider Phase Offset Section ....................................37 Changes to Individual Clock Output Power-Down Section .....39 Changes to Individual Circuit Block Power-Down Section......39 Changes to Soft Reset via the Serial Port Section .......................40 Changes to Multichip Synchronization Section..........................40 Changes to Serial Control Port Section .......................................41 Changes to Serial Control Port Pin Descriptions Section .........41 Changes to General Operation of Serial Control Port Section .......................................................................41 Added Framing a Communication Cycle with CSB Section ....41 Added Communication Cycle—Instruction Plus Data Section.....................................................................................41 Changes to Write Section...............................................................41 Changes to Read Section................................................................42 Changes to Instruction Word (16 Bits) Section ..........................42 Changes to Table 20 ........................................................................42 Changes to MSB/LSB First Transfers Section..............................42 Added Figure 52; Renumbered Sequentially...............................44 Changes to Table 23 ........................................................................45 Changes to Table 24 ........................................................................47 Changes to Power Supply...............................................................54 4/05—Revision 0: Initial Version |
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