AD9511SLASHPCB datasheet(40/60 Pages) AD

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AD9511

Rev. A | Page 40 of 60

Synchronization of two or more AD9511s requires a fast clock

and a slow clock. The fast clock can be up to 1 GHz and may be

the clock driving the master AD9511 CLK1 input or one of the

outputs of the master. The fast clock acts as the input to the

distribution section of the slave AD9511 and is connected to its

CLK1 input. The PLL may be used on the master, but the slave

PLL is not used.

RESET MODES

The AD9511 has several ways to force the chip into a reset

condition.

Power-On Reset—Start-Up Conditions when VS is

Applied

A power-on reset (POR) is issued when the VS power supply is

turned on. This initializes the chip to the power-on conditions

that are determined by the default register settings. These are

indicated in the default value column of Table 23.

The slow clock is the clock that is synchronized across the two

chips. This clock must be no faster than one-fourth of the fast

clock, and no greater than 250 MHz. The slow clock is taken

from one of the outputs of the master AD9511 and acts as the

REFIN (or CLK2) input to the slave AD9511. One of the

outputs of the slave must provide this same frequency back to

the CLK2 (or REFIN) input of the slave.

Asynchronous Reset via the FUNCTION Pin

As mentioned in the FUNCTION Pin section, a hard reset,

RESETB: 58h<6:5> = 00b (Default), restores the chip to the

default settings.

Multichip synchronization is enabled by writing to Register

58h<0> = 1b on the slave AD9511. When this bit is set, the

STATUS pin becomes the output for the SYNC signal. A low

signal indicates an in-sync condition, and a high indicates an

out-of-sync condition.

Soft Reset via the Serial Port

The serial control port allows a soft reset by writing to

soft reset. This restores the default values to the internal

registers, except for Register 00h itself.

the maximum separation of the slow clock edges that are

considered synchronized. When 58h<1> = 0b (default), the

slow clock edges must be coincident within 1 to 1.5 high speed

clock cycles. If the coincidence of the slow clock edges is closer

than this amount, the SYNC flag stays low. If the coincidence of

the slow clock edges is greater than this amount, the SYNC flag

is set high. When Register 58h<1> = 1b, the amount of

coincidence required is 0.5 fast clock cycles to 1 fast clock

cycles.

This bit is not self-clearing. The bit must be written to

00h<5> = 0b for the operation of the part to continue.

SINGLE-CHIP SYNCHRONIZATION

SYNCB—Hardware SYNC

The AD9511 clocks can be synchronized to each other at any

time. The outputs of the clocks are forced into a known state

with respect to each other and then allowed to continue

clocking from that state in synchronicity. Before a

synchronization is done, the FUNCTION Pin must be set as the

SYNCB: 58h<6:5> = 01b input (58h<6:5> = 01b).

Synchronization is done by forcing the FUNCTION pin low,

creating a SYNCB signal and then releasing it.

Whenever the SYNC flag is set (high), indicating an out-of-sync

condition, a SYNCB signal applied simultaneously at the

FUNCTION pins of both AD9511s brings the slow clocks into

synchronization.

See the SYNCB: 58h<6:5> = 01b section for a more detailed

description of what happens when the SYNCB: 58h<6:5> = 01b

signal is issued.

AD9511

MASTER

FAST CLOCK

<1GHz

SLOW CLOCK

<250MHz

AD9511

SLAVE

FAST CLOCK

<1GHz

SLOW

CLOCK

<250MHz

SYNC

DETECT

CLK2

REFIN

OUTY

OUTM

OUTN

FSYNC

STATUS

(SYNC)

FUNCTION

(SYNCB)

FUNCTION

(SYNCB)

SYNCB

CLK1

Soft SYNC—Register 58h<2>

A soft SYNC may be issued by means of a bit in the Register

58h<2>. This soft SYNC works the same as the SYNCB, except

that the polarity is reversed. A 1 written to this bit forces the

clock outputs into a known state with respect to each other.

When a 0 is subsequently written to this bit, the clock outputs

continue clocking from that state in synchronicity.

MULTICHIP SYNCHRONIZATION

The AD9511 provides a means of synchronizing two or more

AD9511s. This is not an active synchronization; it requires user

monitoring and action. The arrangement of two AD9511s to be

synchronized is shown in Figure 43.

Figure 43. Multichip Synchronization

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