AD9511SLASHPCB datasheet(14/60 Pages) AD

14 / 60 page

AD9511

Rev. A | Page 14 of 60

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

CLK1 = 400 MHz

555

fs rms

Calculated from SNR of ADC method;

FC = 100 MHz with AIN = 170 MHz

CMOS (OUT3) = 100 MHz (B Output On)

Divide Ratio = 4

All LVPECL = 50 MHz

Interferer(s)

CMOS (OUT4) = 50 MHz (B Output On)

Interferer(s)

DELAY BLOCK ADDITIVE TIME JITTER1

Incremental additive jitter

100 MHz Output

Delay FS = 1 ns (1600 μA, 1C) Fine Adj. 00000

0.61

Delay FS = 1 ns (1600 μA, 1C) Fine Adj. 11111

0.73

Delay FS = 2 ns (800 μA, 1C) Fine Adj. 00000

0.71

Delay FS = 2 ns (800 μA, 1C) Fine Adj. 11111

1.2

Delay FS = 3 ns (800 μA, 4C) Fine Adj. 00000

0.86

Delay FS = 3 ns (800 μA, 4C) Fine Adj. 11111

1.8

Delay FS = 4 ns (400 μA, 4C) Fine Adj. 00000

1.2

Delay FS = 4 ns (400 μA, 4C) Fine Adj. 11111

2.1

Delay FS = 5 ns (200 μA, 1C) Fine Adj. 00000

1.3

Delay FS = 5 ns (200 μA, 1C) Fine Adj. 11111

2.7

Delay FS = 11 ns (200 μA, 4C) Fine Adj. 00000

2.0

Delay FS = 11 ns (200 μA, 4C) Fine Adj. 00100

2.8

1 This value is incremental. That is, it is in addition to the jitter of the LVDS or CMOS output without the delay. To estimate the total jitter, the LVDS or CMOS output jitter

should be added to this value using the root sum of the squares (RSS) method.

PLL AND DISTRIBUTION PHASE NOISE AND SPURIOUS

Table 7.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

PHASE NOISE AND SPURIOUS

Depends on VCO/VCXO selection. Measured at LVPECL

clock outputs; ABP = 6 ns; ICP = 5 mA; Ref = 30.72 MHz.

VCXO = 245.76 MHz,

FPFD = 1.2288 MHz; R = 25, N = 200

VCXO is Toyocom TCO-2112 245.76.

245.76 MHz Output

Divide by 1.

Phase Noise @100 kHz Offset

<−145

dBc/Hz

Dominated by VCXO phase noise.

Spurious

<−97

dBc

First and second harmonics of FPFD.

Below measurement floor.

61.44 MHz Output

Divide by 4.

Phase Noise @100 kHz Offset

<−155

dBc/Hz

Dominated by VCXO phase noise.

Spurious

<−97

dBc

First and second harmonics of FPFD.

Below measurement floor.

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