AD9511SLASHPCB datasheet(29/60 Pages) AD

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AD9511

Rev. A | Page 29 of 60

FUNCTIONAL DESCRIPTION

OVERALL

Figure 33 shows a block diagram of the AD9511. The chip

combines a programmable PLL core with a configurable clock

distribution system. A complete PLL requires the addition of a

suitable external VCO (or VCXO) and loop filter. This PLL can

lock to a reference input signal and produce an output that is

related to the input frequency by the ratio defined by the

programmable R and N dividers. The PLL cleans up some jitter

from the external reference signal, depending on the loop

bandwidth and the phase noise performance of the VCO

(VCXO).

The output from the VCO (VCXO) can be applied to the clock

distribution section of the chip, where it can be divided by any

integer value from 1 to 32. The duty cycle and relative phase of

the outputs can be selected. There are three LVPECL outputs

(OUT0, OUT1, and OUT2) and two outputs that can be either

LVDS or CMOS level outputs (OUT3 or OUT4). OUT4 can

also make use of a variable delay block.

Alternatively, the clock distribution section can be driven

directly by an external clock signal, and the PLL can be powered

off. Whenever the clock distribution section is used alone, there

is no clock clean-up. The jitter of the input clock signal is

passed along directly to the distribution section and may

dominate at the clock outputs.

PLL SECTION

The AD9511 consists of a PLL section and a distribution

section. If desired, the PLL section can be used separately from

the distribution section.

The AD9511 has a complete PLL core on-chip, requiring only

an external loop filter and VCO/VCXO. This PLL is based on

the ADF4106, a PLL noted for its superb low phase noise

performance. The operation of the AD9511 PLL is nearly

identical to that of the ADF4106, offering an advantage to those

with experience with the ADF series of PLLs. Differences

include the addition of differential inputs at REFIN and CLK2,

and a different control register architecture. Also, the prescaler

has been changed to allow N as low as 1. The AD9511 PLL

implements the digital lock detect feature somewhat differently

than the ADF4106 does, offering improved functionality at

higher PFD rates. See the Register Map Description section.

PLL Reference Input—REFIN

The REFIN/REFINB pins can be driven by either a differential

or a single-ended signal. These pins are internally self-biased so

that they can be ac-coupled via capacitors. It is possible to dc-

couple to these inputs. If REFIN is driven single-ended, the

unused side (REFINB) should be decoupled via a suitable

capacitor to a quiet ground. Figure 34 shows the equivalent

circuit of REFIN.

REFIN

REFINB

150

10k

12k

10k

Figure 34. REFIN Equivalent Circuit

VCO/VCXO Clock Input—CLK2

The CLK2 differential input is used to connect an external VCO

or VCXO to the PLL. Only the CLK2 input port has a

connection to the PLL N divider. This input can receive up to

1.6 GHz. These inputs are internally self-biased and must be ac-

coupled via capacitors.

Alternatively, CLK2 may be used as an input to the distribution

section. This is accomplished by setting Register 45h<0> = 0b.

The default condition is for CLK1 to feed the distribution section.

CLOCK INPUT

STAGE

CLK

CLKB

2.5k

Figure 35. CLK1, CLK2 Equivalent Input Circuit

PLL Reference Divider—R

The REFIN/REFINB inputs are routed to reference divider, R,

which is a 14-bit counter. R may be programmed to any value

from 1 to 16383 (a value of 0 results in a divide by 1) via its

control register (OBh<5:0>, OCh<7:0>). The output of the R

divider goes to one of the phase/frequency detector inputs. The

maximum allowable frequency into the phase, frequency

detector (PFD) must not be exceeded. This means that the

REFIN frequency divided by R must be less than the maximum

allowable PFD frequency. See Figure 34.

VCO/VCXO Feedback Divider—N (P, A, B)

The N divider is a combination of a prescaler, P, (3 bits) and two

counters, A (6 bits) and B (13 bits). Although the AD9511’s PLL

is similar to the ADF4106, the AD9511 has a redesigned

prescaler that allows lower values of N. The prescaler has both a

dual modulus (DM) and a fixed divide (FD) mode. The

AD9511 prescaler modes are shown in Table 14.

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