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AD9511/PCB 数据表(PDF) 10 Page - Analog Devices

部件名 AD9511/PCB
功能描述  1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs
PDF  60 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD9511/PCB 数据表(HTML) 10 Page - Analog Devices

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AD9511
Rev. A | Page 10 of 60
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
CLK1-TO-LVDS ADDITIVE PHASE NOISE
Distribution Section only; does not
include PLL or external VCO/VCXO
CLK1 = 622.08 MHz, OUT= 622.08 MHz
Divide Ratio = 1
@ 10 Hz Offset
−100
dBc/Hz
@ 100 Hz Offset
−110
dBc/Hz
@ 1 kHz Offset
−118
dBc/Hz
@ 10 kHz Offset
−129
dBc/Hz
@ 100 kHz Offset
−135
dBc/Hz
@ 1 MHz Offset
−140
dBc/Hz
>10 MHz Offset
−148
dBc/Hz
CLK1 = 622.08 MHz, OUT = 155.52 MHz
Divide Ratio = 4
@ 10 Hz Offset
−112
dBc/Hz
@ 100 Hz Offset
−122
dBc/Hz
@ 1 kHz Offset
−132
dBc/Hz
@ 10 kHz Offset
−142
dBc/Hz
@ 100 kHz Offset
−148
dBc/Hz
@ 1 MHz Offset
−152
dBc/Hz
>10 MHz Offset
−155
dBc/Hz
CLK1 = 491.52 MHz, OUT = 245.76 MHz
Divide Ratio = 2
@ 10 Hz Offset
−108
dBc/Hz
@ 100 Hz Offset
−118
dBc/Hz
@ 1 kHz Offset
−128
dBc/Hz
@ 10 kHz Offset
−138
dBc/Hz
@ 100 kHz Offset
−145
dBc/Hz
@ 1 MHz Offset
−148
dBc/Hz
>10 MHz Offset
−154
dBc/Hz
CLK1 = 491.52 MHz, OUT = 122.88 MHz
Divide Ratio = 4
@ 10 Hz Offset
−118
dBc/Hz
@ 100 Hz Offset
−129
dBc/Hz
@ 1 kHz Offset
−136
dBc/Hz
@ 10 kHz Offset
−147
dBc/Hz
@ 100 kHz Offset
−153
dBc/Hz
@ 1 MHz Offset
−156
dBc/Hz
>10 MHz Offset
−158
dBc/Hz
CLK1 = 245.76 MHz, OUT = 245.76 MHz
Divide Ratio = 1
@ 10 Hz Offset
−108
dBc/Hz
@ 100 Hz Offset
−118
dBc/Hz
@ 1 kHz Offset
−128
dBc/Hz
@ 10 kHz Offset
−138
dBc/Hz
@ 100 kHz Offset
−145
dBc/Hz
@ 1 MHz Offset
−148
dBc/Hz
>10 MHz Offset
−155
dBc/Hz
CLK1 = 245.76 MHz, OUT = 122.88 MHz
Divide Ratio = 2
@ 10 Hz Offset
−118
dBc/Hz
@ 100 Hz Offset
−127
dBc/Hz
@ 1 kHz Offset
−137
dBc/Hz
@ 10 kHz Offset
−147
dBc/Hz



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