AD9511SLASHPCB datasheet(52/60 Pages) AD

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AD9511

Rev. A | Page 52 of 60

Reg.

Addr.

(Hex)

Bit(s) Name

Description

<3:0> Divider High

Number of Clock Cycles Divider Output Stays High.

OUT0

(4C)

(OUT1)

(4E)

(OUT2)

(50)

(OUT3)

(52)

(OUT4)

<7:4> Divider Low

Number of Clock Cycles Divider Output Stays Low.

OUT0

(4C)

(OUT1)

(4E)

(OUT2)

(50)

(OUT3)

(52)

(OUT4)

<3:0> Phase Offset

Phase Offset (Default = 0000b).

OUT0

(4D)

(OUT1)

(4F)

(OUT2)

(51)

(OUT3)

(53)

(OUT4)

<4>

Start

Selects Start High or Start Low.

OUT0

(Default = 0b).

(4D)

(OUT1)

(4F)

(OUT2)

(51)

(OUT3)

(53)

(OUT4)

<5>

Force

Forces Individual Outputs to the State Specified in Start (Above).

This Function Requires That Nosync (Below) Also Be Set (Default = 0b).

OUT0

(4D)

(OUT1)

(4F)

(OUT2)

(51)

(OUT3)

(53)

(OUT4)

<6>

Nosync

Ignore Chip-Level Sync Signal (Default = 0b).

OUT0

(4D)

(OUT1)

(4F)

(OUT2)

(51)

(OUT3)

(53)

(OUT4)

<7>

Bypass Divider

Bypass and Power-Down Divider Logic; Route Clock Directly to Output (Default = 0b).

OUT0

(4D)

(OUT1)

(4F)

(OUT2)

(51)

(OUT3)

(53)

(OUT4)

54 (55)

(56) (57)

<7:0>

Not Used.

<0>

SYNC Detect

Enable

1 = Enable SYNC Detect (Default = 0b).

<1>

SYNC Select

1 = Raise Flag if Slow Clocks Are Out-of-Sync by 0.5 to 1 High Speed Clock Cycles.

0 (Default) = Raise Flag if Slow Clocks Are Out-of-Sync by 1 to 1.5 High Speed Clock Cycles.

AD9511/PCB 数据表(PDF) 52 Page - Analog Devices

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AD9511/PCB 数据表(PDF) 52 Page - Analog Devices

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