Data Sheet
RSC-4128
11
P/N 80-0206-R
© 2006 Sensory Inc.
Bits [4:0] of the “bank” register determine which physical bank of 64 bytes is logically mapped to addresses 080H-
0BFH. When a logical address falls in the range of 080H-0BFH, the lower 6 bits of the logical address (64 byte
address) are combined with the “bank” register bits used as the upper 5 bits of an 11-bit physical address. This
physical address is used to address 768 bytes (12 banks) of physical bank RAM. (Note: 4 bits are required by the
“bank” register to address 12 banks, but 5 bits are provided to allow for possible increases in the register RAM for
future RSC family members.) Here is a table that illustrates this banking scheme:
Mapping of logical addresses 080H-0BFH (“bank” register FC is used)
register FC [4:0]
Physical Bank RAM
register FC [4:0]
Physical Bank RAM
00H (Bank 0)
00-3FH
08H (Bank 8)
200-23FH
01H (Bank 1)
40-7FH
09H (Bank 9)
240-27FH
02H (Bank 2)
80-BFH
0AH (Bank A)
280-2BFH
03H (Bank 3)
C0-FFH
0BH (Bank B)
2C0-2FFH
04H (Bank 4)
100-13FH
0CH
--- (unimplemented)
05H (Bank 5)
140-17FH
0DH
--- (unimplemented)
06H (Bank 6)
180-1BFH
0EH
--- (unimplemented)
07H (Bank 7)
1C0-1FFH
0FH
--- (unimplemented)
NOTE: If a value other than those indicated above is used in the “bank” register, an undefined state will result.
User RAM is assigned both in directly addressed register RAM space and in banked register RAM space.
Addresses 03AH-07FH (70 bytes) of directly addressed register RAM and Banks 0, A and B (192 bytes) of banked
register RAM are assigned for a total of 262 bytes of User RAM.
See the “Special Functions Registers Summary” for details on the contents of SFRs.
L1 Vector Accelerator/Multiplier
A variety of macros are provided by Sensory that manipulate the L1 Vector Accelerator to provide signed and
unsigned multiplication functions.
See the “FluentChip™ Technology Library Manual” for information on these
macros and their application.
The L1/Multiplier unit may be independently powered down by programming the register D6.Bit 4 to “0” (“clkExt”
register, “L1clk_on” bit).
Digital Filter
The RSC-4128 has a Digital Filter engine capable of dividing up a frequency range into several smaller ranges. It
is also capable of reporting characteristics of each range to the RSC-4128 processor. The configuration of the
Digital Filter engine and access to signal characteristics generated are enabled by technology modules which are
available from Sensory “Technology Support” upon request.
Power and Wakeup Control
The typical Active Supply Current is realized when operating with a main clock rate of 14.32 MHz at 3V and all I/O
configured to the high-Z state. Lowering clock frequency reduces active power consumption, although FluentChip™
technology typically requires a 14.32 MHz clock.
Two supply current power-down modes are available to power down the RSC core – Sleep and Idle modes. In
Sleep mode everything is stopped, and only an I/O event can initiate a wake-up. In Idle mode OSC2 and Timer2
continue to run, and an I/O Wakeup or Timer2 interrupt request caused by overflow can generate a wake-up.
A low power mode is also available by using Idle with Audio Wakeup. In this mode the Audio Wakeup circuitry will
wake the chip from Idle mode. A somewhat higher supply current is consumed in this mode due to the Audio
Wakeup logic and an active microphone. An I/O event, Timer2 interrupt request caused by overflow, or audio event
can generate a wake-up from this mode. The current consumed by the Audio Wakeup logic is typically 40uA.
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