80-0206-R datasheet(26/49 Pages) ETC1

26 / 49 page

RSC-4128

Data Sheet

P/N 80-0206-R

The interrupt vector is generated as a 20-bit address. The low 16 bits are derived from the execution table above,

and the high 4 bits are selected as a normal code fetch as described in the “Memory Addressing” section.

Specifically, the “cb1” bit is not touched by the interrupt.

If the corresponding mask register bit is clear, the “irq” bit will not cause an interrupt. However, it can be polled by

reading the “irq” register.

“irq” bits can be cleared by writing a “0” to the corresponding bit at register FE (the “irq” register). “irq” bits cannot

be set by writing to register FE. Writing a “1” to that register is a NO-OP.

The “irq” bits must be cleared within the interrupt handler by an explicit write to the “irq” register rather than by an

implicit interrupt acknowledge.

PLEASE NOTE:

Clear interrupts this way –

mov irq, #bitmask

; CORRECT

Not this way –

And irq, #bitmask

; INCORRECT

The “and” instruction is not a single action. The “and” instruction is a read-modify-write action. If an interrupt

occurs during an “and irq” operation the interrupt will be cleared before it is seen, possibly disabling the interrupt

until the system is reset. Because one cannot directly set or clear bits in the “irq” register, use “mov irq” as a safe

and effective single action to clear bits in the “irq” register. Use it the way you would use an “and” instruction to

operate on other registers.

NOTE: Bit2 and Bit5 of the “irq” register should always be written as “1” when clearing other “irq” bits, to avoid

conflicts with the Technology code use of these bits.

In Idle mode, Timer2 continues to operate even when the rest of the RSC-4128 is powered-down. An overflow

from Timer2 will set the corresponding “irq” flag even when there is no clock input to the processor. Note that the

Timer2 “irq” bit (register FE.Bit1) must be cleared prior to powering down to allow the wakeup interrupt request to

occur. This may also lead to normal interrupt processing once the processor is active, if the Timer 2 “imr” bit is set

(register FD.Bit1). This interrupt response is unique from, and may be in addition to, the T2 Wakeup.

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