RSC-4128
Data Sheet
36
P/N 80-0206-R
© 2006 Sensory Inc.
ROTATE Group Instructions
Rotate group instructions apply only directly to register space SRAM locations. The carry flag is affected by these
instructions, but the sign and zero flags are unaffected.
Instruction Opcode Operand 1 Operand 2 Description
Bytes
Cycles +Cycles/Waitstate
RL
30
dest
-
rotate left, c set from b7
2
5
2
RR
31
dest
-
rotate right, c set from b0 2
5
2
RLC
32
dest
-
rotate left through carry
2
5
2
RRC
33
dest
-
rotate right through carry 2
5
2
SHL
34
dest
-
shift left, c set from b7,
b0=0
2
5
2
SHR
35
dest
-
shift right, c set from b0,
b7=0
2
5
2
SAR
36
dest
-
shift right arithmetic, c
set from b0, b7
duplicated
2
5
2
BRANCH Group Instructions
The branch instructions use direct address values rather than offsets to define the target address of the branch.
This implies that binary code containing branches is not relocatable. However, object code produced by the RSC-
4128 assembler contains address references that are resolved at link time, so .OBJ modules are relocatable. The
indirect jump instruction uses an 8-bit operand (“@dest”) to designate an SRAM register pointer to the 16-bit target
address. The “dest” pointer register must be at an even address. The LOW byte of the target address is contained
at the pointer address, and the HIGH byte of the target address is contained at the pointer address+1.
Instruction Opcode Operand 1 Operand 2 Description
Bytes Cycles +Cycles/Waitstate
JC
20
dest low
dest high
jump on carry = 1
3
3
3
JNC
21
dest low
dest high
jump on carry = 0
3
3
3
JZ
22
dest low
dest high
jump on zflag = 1
3
3
3
JNZ
23
dest low
dest high
jump on zflag = 0
3
3
3
JS
24
dest low
dest high
jump on sflag = 1
3
3
3
JNS
25
dest low
dest high
jump on sflag = 0
3
3
3
JMP
26
dest low
dest high
jump unconditional
3
3
3
CALL
27
dest low
dest high
direct subroutine call 3
3
3
RET
28
-
-
return from call
1
2
1
IRET
29
-
-
return from interrupt 1
2
1
JMPR
2A
@dest
-
jump indirect
2
4
2
ARITHMETIC/LOGICAL Group Instructions
Arithmetic and logical group instructions apply only to Register Space SRAM locations. The results of the
instruction are always written directly to the SRAM “dest” register. The exceptions are TM and CP instructions,
which do not write the result to the “dest” register and only update the flags register based on the operation’s
outcome. All but the INCrement and DECrement instructions have both register source and immediate source
forms.
In each of the following instructions the sign and zero flags are updated based on the result of the operation. The
carry flag is updated by the arithmetic operations (ADD, ADC, SUB, SUBC, CP, INC, DEC) but it is not affected by
the logical operations (AND, TM, OR, XOR). Note: the carry is set high by SUB, CP, SUBC and DEC when a
borrow is generated.
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