Data Sheet
RSC-4128
9
P/N 80-0206-R
© 2006 Sensory Inc.
Using the RSC-4128
Creating applications using the RSC-4128 requires the development of electronic circuitry, software code, and
speech/music data files. Software code for the RSC-4128 can be developed using a complete suite of RSC-4128
development tools including In-Circuit Emulator, C Compiler, and “push button” tools for speech recognition and
synthesis data files. Sensory provides free design reviews of customer applications to assist in the speech dialog
and speech I/O design.
Sensory also offers application development services.
For more information about
development tools and services, please contact Sensory.
When using the RSC-4128 macro blocks such as the AFE, digital filters, L1, etc, for purposes other than as
intended in the FluentChip™ technology modules, in applications that will also use FluentChip™ technologies, care
must be taken to avoid conflicts that may cause adverse impact on functionality.
Contact Sensory Technical
Support for help in avoiding these conflicts.
Instruction Set
The instruction set for the RSC-4128 has 60 instructions comprising 13 move, 7 rotate, 11 branch, 22 arithmetic,
and 7 miscellaneous instructions. All instructions are 3 bytes or fewer and no instruction requires more than 10
clock cycles (plus wait states) to execute. (see “Instruction Set Opcodes and Timing Details” for detailed
descriptions)
Flags
The “flags” register (register FF) has bits that are set/cleared by arithmetic/logical instructions, a trap enable bit set
under program control, a read-only stack overflow bit cleared at power on and set by stack wrap around, and the
Global Interrupt Enable bit:
0FFH
R/W
“flags”
Bit 7:
carry
Bit 6:
zero
(set = 1 when result of arith/log instruction is 0)
Bit 5:
sign
(set = 1 when result of arith/log instruction has msb high)
Bit 4:
trap
Bit 3:
stkoflo
(read-only, initialized to 0, set to 1 on stack overflow)
Bit 3:
stkfull
(read-only, initialized to 0, set to 1 on stack full)
Bit 1:
(unused)
Bit 0:
gie
(Global Interrupt Enable)
NOTE: The “trap” bit must be left written as “0”.
Flags Hold
The “flagsHold” register (register CF) stores the “flags” value when an interrupt occurs. Unlike previous RSC chips,
the RSC-4128 processor has read/write access to “flagsHold” for multi-tasking purposes. Since the “flags” register
is restored from the “flagsHold” register upon return from interrupt, the “stkoflo” and “stkfull” bits are omitted from
the “flagsHold” register to prevent inadvertent clearing of these bits.
0CFH
R/W
“flagsHold”
Bit 7:
carry
Bit 6:
zero
Bit 5:
sign
Bit 4:
trap
Bit 3:
(unused – reads 0)
Bit 2:
(unused – reads 0)
Bit 1:
(unused – reads 0)
Bit 0:
gie
NOTE: The “trap” bit must be left written as “0”.
See the discussion in “Interrupts” section relating to the value of “gie” stored in the “flagsHold” register when an
interrupt occurs during execution of an instruction that clears the “gie” bit.
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