RSC-4128
Data Sheet
22
P/N 80-0206-R
© 2006 Sensory Inc.
Prescaler value
Divisor
Prescaler value
Divisor
0000
1
1000
256
0001
2
1001
512
0010
4
1010
1024
0011
8
1011
2048
0100
16
1100
4096
0101
32
1101
8192
0110
64
1110
16384
0111
128
1111
32768
The resolution of T1 and T3 is 8 bits, but the range is 23 bits. The longest interval that can be timed by T1 or T3 is
2^15*256 clocks = 9.3 seconds.
The 4-bit prescaler for T1 is in the Clock Extensions Register, (register D6.Bits[3:0]). The 4-bit prescaler for T3 is in
the Timer3 Control Register (register D9.Bits[3:0]).
In addition to its timing capability, T3 can also be configured as a counter of external events. In this configuration it
uses either the rising or falling edge of a signal applied to I/O pin P0.1. The selected transition is internally
synchronized to CLK1. The maximum external count rate for T3 is 447KHz.
The Timer3 Control Register contains the counting/timing options for T3. The register is write-only. Bits[6:4] provide
configuration control.
Bit6
Bit5
Bit4
timer source
Configuration
x
0
0
T3CLK
timer
0
0
1
T3CLK
timer gated by P0.1 LOW
1
0
1
T3CLK
timer gated by P0.1 HIGH
0
1
x
P0.1
count P0.1 events, rising edge
1
1
x
P0.1
count P0.1 events, falling edge
Bit 7
0: disable T3 and prescaler from counting/timing
1: enable T3
cleared by reset.
Bit 6
0: use rising edge for external event counting
use LOW state on pin P0.1 for timer gating
1: use falling edge for external event counting
use HIGH state on pin P0.1 for timer gating
cleared by reset
Bit 5
0: use internal T3CLK for source (timing)
1: use external events on pin P0.1 for source (counting)
cleared by reset
Bit 4
0: normal operation
1: T3 is gated by pin P0.1 according to Bit6
cleared by reset.
Bit 3:0
Encoded prescaler for T3. (See prescaler table above).
cleared by reset.
T1 and T3 can generate interrupts upon overflow by setting register FD.Bit0=1 and Bit4=1, respectively. (see
“Interrupts” section)
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