RSC-4128
Data Sheet
18
P/N 80-0206-R
© 2006 Sensory Inc.
Access of external ROM space is always controlled by these wait state bits. Internal ROM space and all external
R/W space accesses may also controlled by these bits, unless otherwise selected by bits in the clock extension
register (register D6, “clkExt”) The internal RAMs always operate with zero wait states.
Register D6 provides for extended control of some clocks derived from OSC1 for producing additional timer scaling
or specialized wait states. When Bit 5 is set, it overrides the “bank” register control of wait states during MOVX
instructions which access external read/write memory (register D2.Bit4=1), and forces a fixed value of 4 wait states
(nominal 350ns access). When Bit 7 is set, it overrides the “bank” register control of wait states during internal
ROM accesses and forces zero wait states.
Using these controls, various memory access speeds may be
accommodated within one application.
Bit 5
0: Certain MOVX* instructions use the Wait State divisor in register FC.Bits[7:5]
1:Certain MOVX* use fixed 4 Wait States (nominal 350nsec access)
Cleared by reset
Bit 6
0: MT timer clock is disabled
1: MT timer clock I s enabled
Cleared by reset
Bit 7
0: Accesses to internal ROM use the Wait State divisor set in register 0FCh[7:5]
1: Accesses to internal ROM use selected CLK (no wait states)
Cleared by reset.
* MOVX accessing external read-write memory (“rw”; register D2.Bit4=1).
Instruction
Opcode
Operand 1
Operand 2
Description
Bytes
Cycles
+Cycles/
Waitstate
MOV
10
dest
Source
register to register
3
5
3
MOV
11
@dest
Source
register to register-indirect
3
5
3
MOV
12
dest
@source
register-indirect to register
3
6
3
MOV
13
dest
#immed
immediate data to register
3
4
3
MOVC
14
dest
@source
code space to register
3
7
4
MOVC
15
@dest
Source
register to code space
3
8
4
MOVX
16
dest
@source
data space to register
3
7
4*
MOVX
17
@dest
Source
register to data space
3
8
4*
POP
18
dest
@++source
register to register data
stack pop (source pre-
incremented)
3
10
3
PUSH
19
@dest--
Source
register to register data
stack push (dest post-
decremented)
3
9
3
MOVY
1A
dest
@source
RAMY to register, indirect
3
7
3
MOVY
1B
@dest
source
register to RAMY, indirect
3
7
3
MOVD
1C
dest_pair
source_pair
register to register, direct,
16-bit MOV
3
7
3
*MOVX instructions will have the number of wait states selected by register FC.Bits[7:5], unless register D2.Bit4
and register D6.Bit5 are set, in which case the number of wait states is fixed at 4.
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