Data Sheet
RSC-4128
5
P/N 80-0206-R
© 2006 Sensory Inc.
RSC-4128 Architecture
The RSC-4128 is a highly integrated speech and analog I/O mixed signal processor that combines:
8-bit microcontroller with enhanced instructions and interrupt control, superior register architecture, independent
Digital Filter engine and “L1” Vector Math Accelerator
On-chip ROM and RAM (4.8 Kbytes), and the ability to address off-chip RAM, ROM, EPROM or Flash.
Input microphone preamp and 16 bit Analog-to-Digital Converter (ADC) for speech and audio/analog input
10 bit Digital-to-Analog Converter (DAC), and 10 bit Pulse Width Modulator (PWM) to directly drive a speaker or
other analog device
Low power Audio Wakeup from power down mode, when a selected audio event, such as clap or whistle, occurs
The RSC-4128 has 20-bit address
and 8-bit data buses for interfacing
with external memory. It includes an
-XM input pin capable of enabling or
disabling the internal ROM.
NOTE: Neither the -XM input pin nor
the extended memory buses are
available
on
64-lead
LQFP
packaged versions of the RSC-4128
with
internal
ROM.
These
are
available on the die and 100 LQFP
versions.
Three bi-directional ports provide 24
configurable, general-purpose I/O
pins to communicate with or control
external devices with a variety of
source and sink currents. Up to 4 of
these
I/O
may
be
used
as
programmable Analog Comparator
inputs. 16 may be used as I/O
wakeup.
The
RSC-4128
has
a
high
frequency (14.32 MHz) clock as well
as a low frequency (32,768 Hz)
clock. The processor clock can be
selected from either source, with a
selectable divider value. The device
performs speech recognition when
running at 14.32 MHz. The RSC-
4128 also supports programmable
wait states to allow the use of
slower memory.
OSC1 is a very low-cost 3.58 MHz
crystal oscillator that is used by a
4X PLL to generate the 14.32MHz
clock. The OSC2 oscillator provides the options of using an external crystal or its own internal RC devices (no
external components required for the internal RC mode).
RSC-4128 Internal Block Diagram
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