CS5920 datasheet(117/160 Pages) AMCC

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S5920 – PCI Product

Revision 1.01 – November 28, 2005

AMCC Confidential and Proprietary

DS1596

117

Data Book

mation for the current PCI cycle. When the PCI bus

performs burst accesses, the APTA register is incre-

mented by the S5920 to reflect the address of the

current data phase. PTNUM[1:0] is used to determine

what region owns the current data access.

For PCI writes to the Add-On, the S5920 transfers

data from the PCI bus into the Pass-Thru Write FIFO.

When the Pass-Thru write FIFO becomes not empty,

the S5920 asserts the Pass-Thru status signals to indi-

cate to the Add-On that data is present. The Add-On

logic will then read data from the FIFO. The S5920

continues accepting write data from the PCI initiator as

long as the 8x32 FIFO is not full.

For PCI reads from the Add-On, the S5920 asserts the

Pass-Thru status signals to indicate to the Add-On that

data is required. The Add-On logic should write the

requested data into the Pass-Thru Read FIFO. The

S5920 will assert TRDY# to the PCI bus after the Add-

On logic has transferred data into the FIFO. As long as

data is in the FIFO, and PCI read data is still

requested, TRDY# will continue to be asserted. If the

Add-On cannot provide data quickly enough, the

S5920 signals a disconnect to the PCI bus. This

allows the PCI bus to perform other tasks, rather than

waiting for a slow target. The S5920 will prefetch data

if enabled.

Pass-Thru Status/Control Signals

The S5920 Pass-Thru registers are accessed using

the Add-On register access pins. The Pass-Thru

Address Register (APTA) can, optionally, be accessed

using a single, direct access input, PTADR#. Pass-

Thru cycle status indicators are provided to control

Add-On logic based on the type of Pass-Thru access

occurring (single cycle, burst, etc.). The signals in the

table above are provided for Pass-Thru operation:

BUS INTERFACE

The Pass-Thru data channel allows PCI initiators to

read or write to resources on the Add-On bus. A PCI

initiator may access the Add-On with single data

phase cycles or multiple data phase bursts. The Add-

On interface implements Pass-Thru status and control

signals used by logic to complete data transfers initi-

ated by the PCI bus. The Pass-Thru interface is

designed to allow Add-On logic to function without

knowledge of PCI bus activity. Add-On logic only

needs to react to the Pass-Thru status signals. The

S5920 PCI device independently interacts with the

PCI initiator to control data flow between the devices.

The following sections describe the PCI and Add-On

bus interfaces. The PCI interface description provides

a basic overview of how the S5920 interacts with the

PCI bus, and may be useful in system debugging. The

Add-On interface description indicates functions

required by Add-On logic and details the Pass-Thru

handshaking protocol.

PCI Bus Interface

The S5920 device examines all PCI bus cycle

addresses. If the address associated with the current

Signal

Function

PTATN#

This output indicates a Pass-Thru access needs servicing.

PTBURST#

This output indicates that the current Pass-Thru access is a PCI burst transfer or a single cycle transfer.

PTBURST# is deasserted immediately after the second to last burst data has been transferred on the PCI

side. PTBURST# is also active during prefetch cycles.

PTNUM[1:0]

These outputs indicate which Pass-Thru region decoded the PCI address.

PTBE[3:0]#

These outputs indicate which data bytes are valid (PCI writes), or requested (PCI reads). See timing dia-

grams for further details. PTBE0# = 0 Byte 0 is valid, PTBE1# = 0 Byte 1 is valid, PTBE# = 0 Byte 2 is valid,

PTBE3# = 0 Byte 3 is valid.

PTWR

This output indicates if the Pass-Thru access is a PCI read or a write.

PTADR#

When asserted, this pin drives the Pass-Thru Address Register contents onto the Add-On data bus. This

input enables the DQ[31:0] data bus to become active immediately. There is NO pipeline delay from PTADR#

to DQ, as there is from RD# to DQ. As result, this is an asychronous input.

PTRDY#

In Passive mode, this input indicates the current Pass-Thru transfer has been has been completed by the

Add-On. In Active mode, this input indicates that wait states are to be inserted for the next transfer.

ADCLK

Input Add-On clock (to synchronize Pass-Thru data register accesses).

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