CS5920 datasheet(113/160 Pages) AMCC

113 / 160 page

S5920 – PCI Product

Revision 1.01 – November 28, 2005

AMCC Confidential and Proprietary

DS1596

113

Data Book

ADD-ON LOCAL BUS INTERFACE

This chapter describes the Add-On Local bus interface

of the S5920. The S5920 is designed to support con-

nection to a variety of microprocessor buses and/or

peripheral devices. The Add-On interface controls

S5920 operation through the Add-On Operation Reg-

isters accessed through the 32 bit local bus.

The Add-On local bus interface is synchronous to

ADCLK. ADCLK is a 0-40 MHz clock input which can

be configured as asynchronous to the PCI clock or

synchronous when connected to the S5920 BPCLK

output. The following sections describe the various

interfaces to the PCI bus and how they are accessed

from the Add-On bus.

ADD-ON INTERFACE SIGNALS

The Add-On bus provides a number of system signals

to allow Add-On logic to monitor PCI bus activity, to

indicate status conditions (interrupts), and to configure

the S5920 Add-On bus.

SYSTEM SIGNALS

BPCLK is a buffered version of the PCI clock. The PCI

clock can operate from 0 MHz to 33 MHz.

SYSRST# is a buffered version of the PCI reset signal,

and may also be toggled by host application software

through bit 24 of the Reset Control Register (RCR).

IRQ# is the PCI interrupt request output to the Add-On

bus. This signal is active low and can indicate multiple

conditions. Add-On interrupts can be generated from

the mailbox interface or to indicate start of BIST. The

conditions which will generate an IRQ# due to mailbox

activity are discussed in the mailbox chapter. The

IRQ# output is deasserted when acknowledged by

writing a 1 to the corresponding interrupt bit in the

Add-On Interrupt Control/Status Register (AINT). See

Table 3.

The PTMODE signal (Pass-Thru Mode) controls the

Pass-Thru interface only. Asserting it will configure the

Pass-Thru in Passive mode and low will configure the

Pass-Thru in Active mode.

ADDINT# is an Add-On interrupt input pin. When

asserted, it will cause the PCI interrupt output pin

(INTA#) to assert. The ADDINT# is a level-sensitive

input. Any number of Add-On peripheral interrupt

sources can drive this input. There must be a pull-up

resistor on the board to pull it high when inactive. This

interrupt has to be enabled by Bit 13 of the INTCSR. It

is the responsibility of the PCI host to clear the inter-

rupt source of ADDINT# in order to have the pending

interrupt deasserted.

The DQMODE signal configures the data path width

for all Add-On Operation register accesses, except for

the Pass-Thru Data and Address registers. When

DQMODE is low, DQ is configured as a 32-bit data

bus. When DQMODE is high, DQ is configured as a

16-bit data bus. For 16-bit operation, BE3# is rede-

fined as ADR1, providing an extra address input, and

BE2# is unused. ADR1 selects the low or high words

of the 32-bit S5920 Add-On Operation Registers.

ADD-ON S5920 REGISTER ACCESSES

The S5920 Add-On bus is very similar to that of a

memory or peripheral device found in a microproces-

sor-based system. A 32-bit data bus with individual

read and write strobes, a chip select and byte enables

are provided.

Registers are synchronous to the Add-On input clock

(ADCLK). The following signals are required to com-

plete a register access to the S5920.

BE[3:0]#

Byte Enable Inputs. These signals identify

which bytes of the DQ bus are valid during Add-

On bus transactions. BE0# indicates valid

DQ[7:0], BE1# a valid DQ[15:8], etc. When DQ is

configured for 16-bit operation, BE2# is not

defined and BE3# becomes ADR1.

ADR[6:2]

Address Register Inputs. These pins

address a specific Add-On Operation Register

within the S5920. When DQ is configured for 16-

bit operation, an additional input, ADR1 is avail-

able to allow the 32-bit operation registers to be

accessed in two 16-bit cycles.

RD#

Read Enable Input.

WR#

Write Enable Input.

SELECT#

Chip Select Input. This input indicates RD#,

WR#, ADR[6:2] and BE[3:0] are valid.

DQ[31:0]

Bi-directional Data Bus. These I/O pins are

the Add-On data bus.

S5920 General Register Accesses

For many Add-On applications, Add-On logic does not

operate at the PCI bus frequency. This is especially

true for Add-On designs implementing a microproces-

sor, which may be operating at a lower or higher

frequency.

The RD# and WR# inputs become enables, using

ADCLK to clock data into and out of registers. All

inputs are sampled on the rising edge of ADCLK.

CS5920 数据表(PDF) 113 Page - Applied Micro Circuits Corporation

CS5920 数据表(HTML) 113 Page - Applied Micro Circuits Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载