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CS5920 数据表(PDF) 112 Page - Applied Micro Circuits Corporation |
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CS5920 数据表(HTML) 112 Page - Applied Micro Circuits Corporation |
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112 / 160 page  S5920 – PCI Product Revision 1.01 – November 28, 2005 AMCC Confidential and Proprietary DS1596 112 Data Book 4. Clear the interrupt source. The Add-On IRQ# signal is deasserted by clearing the interrupt request. The request is cleared by writing a 1 to the appropriate bit. NOTE: For an incoming mailbox interrupt, step 3 involves accessing the mailbox. To allow the incoming mailbox interrupt logic to be cleared, the mailbox status bit must also be cleared. Reading an incoming mailbox clears the status bits. Another option for clearing the status bits is to use the Mailbox Flag Reset bit in the RCR and ARCR registers, but this clears all status bits, not just a single mailbox byte. For outgoing mailbox interrupts, the status bit was already cleared prior to the generation of the interrupt. As a result, the mailbox does not need to be read. AINT Bit 17 Clear Add-On outgoing mailbox interrupt AINT Bit 16 Clear Add-On incoming mailbox interrupt |
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