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CS5920 数据表(PDF) 110 Page - Applied Micro Circuits Corporation |
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CS5920 数据表(HTML) 110 Page - Applied Micro Circuits Corporation |
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110 / 160 page  S5920 – PCI Product Revision 1.01 – November 28, 2005 AMCC Confidential and Proprietary DS1596 110 Data Book Mailbox Interrupts Although polling status is useful in some cases, polling requires continuous actions by the processor. Mailbox inter- rupt capabilities are provided to avoid much of the processor overhead required by continuously polling status bits. The Add-On and PCI interface can each generate interrupts on the incoming mailbox condition and/or the outgoing mailbox condition. These can be individual enabled/disabled. A specific byte in the incoming mailbox and outgoing mailbox is identified to generate the interrupt(s). The tasks required to setup the mailbox interrupts are as follows: Enabling PCI mailbox interrupts: 1. Enable PCI outgoing mailbox interrupts. A specific byte within the outgoing mailboxes is identified to assert INTA# when read by the Add-On interface. 2. Enable PCI incoming mailbox interrupts. A specific byte within the incoming mailboxes is identified to assert INTA# when written by the Add-On interface. Enabling Add-On mailbox interrupts: 1. Enable Add-On outgoing mailbox interrupts. A specific byte within the outgoing mailboxes is identified to assert IRQ# when read by the PCI interface. 2. Enable Add-On incoming mailbox interrupts. A specific byte within the incoming mailboxes is identified to assert IRQ# when written by the PCI interface. With either the Add-On or PCI interface, these two steps can be performed with a single access to the appropriate register. They are shown separately here for clarity. Once interrupts are enabled, the interrupt service routine must access the mailboxes and clear the interrupt source. A particular application may not require all of the steps shown. For instance, a design may only use the incoming mailbox interrupts and not require support for the outgoing mailbox interrupts. The interrupt service rou- tine tasks are as follows: INTCSR Bit 4 Enable outgoing mailbox interrupts INTCSR Bits 1:0 Identify mailbox byte to generate interrupt INTCSR Bit 12 Enable incoming mailbox interrupts INTCSR Bits 9:8 Identify mailbox byte to generate interrupt AINT Bit 12 Enable outgoing mailbox interrupts AINT Bits 9:8 Identify mailbox byte to generate interrupt AINT Bit 4 Enable incoming mailbox interrupts AINT Bits 1:0 Identify mailbox byte to generate interrupt |
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