CS5920 datasheet(124/160 Pages) AMCC

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S5920 – PCI Product

Revision 1.01 – November 28, 2005

AMCC Confidential and Proprietary

DS1596

124

Data Book

Clock 3:

The Add-On latches the address. Data 1 is

driven on the DQ bus as a result of the previous read.

As PTRDY# is sampled asserted, the PTBE# outputs

are updated to indicate which bytes are valid for the

second transfer. The BE[3:0]#, ADR[6:2], and

SELECT# inputs remain driven along with RD# to read

out the next data. PTRDY# remains asserted, indicat-

ing that the second transfer is complete.

Clock 4:

Add-On logic uses the rising edge of this

clock to store DATA1. DATA2 is driven on the DQ bus

as a result of the previous read. As PTRDY# is sam-

pled asserted, the PTBE# outputs are updated to

indicate which bytes are valid for the third transfer.

PTRDY# remains asserted, indicating that the third

transfer is complete.

Clock 5:

Add-On logic uses the rising edge of this

clock to store DATA2. PTBURST# is deasserted indi-

cating that only a single data phase remains. DATA3 is

driven on the Add-On bus. The PTBE# outputs are

updated to indicate which bytes are valid for the last

transfer. PTRDY# remains asserted, indicating that the

current transfer is complete.

Clock 6:

Add-on logic uses the rising edge of this

clock to store DATA3 from the S5920. PTRDY# sam-

pled completes the last data phase. As a result, the

S5920 deasserts PTATN#, and drives DATA4 onto the

DQ bus. As the Add-on sampled PTBURST# deas-

serted and PTATN# asserted, it recognizes that the

previous read was the last one. As a result, the Add-

On deasserts SELECT#, ADR[6:2], BE[3:0]#, RD# and

PTRDY#.

Clock 7:

The Add-on logic stores DATA4 on the rising

edge of this clock. As PTATN# is deasserted, the

Pass-Thru access is complete, and the S5920 can

accept new Pass-Thru accesses starting on the next

clock. The other Pass-Thru signals can also change

state (in anticipation of a new transfer).

Figure 8 illustrates a Passive mode transfer with a

burst of five DWORDs in a PCI to Pass-Thru burst

write with PTRDY# used to insert wait states. In some

applications, Add-On logic may not be required to

transfer data on every ADCLK and can use PTRDY#

to control the data rate transfer. In this example, Add-

On logic latches data every other clock cycle. RD# is

shown deasserted when PTRDY# is deasserted, but

could remain active during the entire Add-On burst. In

this case, the DQ would not go to tri-state between

reads, and the PTBE# outputs would lose some of

their significance (as they would transition one cycle

early as a result of the “unused” read).

Clock 0:

The address is recognized as a PCI write to

Pass-Thru region 0. The PCI bus write address is

stored in the Pass-Thru Address Register. The PCI

bus write data is stored in the S5920 write FIFO. Add-

On bus signals PTATN#, PTBURST#, PTNUM[1:0],

PTWR and PTBE[3:0] will update on the next rising

edge of ADCLK.

CS5920 数据表(PDF) 124 Page - Applied Micro Circuits Corporation

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