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数据搜索系统，热门电子元器件搜索 |
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CS5920 数据表(PDF) 126 Page - Applied Micro Circuits Corporation |
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CS5920 数据表(HTML) 126 Page - Applied Micro Circuits Corporation |
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126 / 160 page  S5920 – PCI Product Revision 1.01 – November 28, 2005 AMCC Confidential and Proprietary DS1596 126 Data Book Clock 1: Pass-Thru signals PTATN#, PTBURST#, PTNUM[1:0], PTWR and PTBE[3:0] are driven to indi- cate what action is required by Add-On logic. These status signals are valid only when PTATN# is active. Add-On logic can decode status signals upon the assertion of PTATN#. PTATN# Asserted. Indicates Pass-Thru access is pending. PTBURST# Asserted. The access has multiple data phases. PTNUM[1:0] 0h. Indicates the access is to Pass-Thru region 3. PTWR Asserted. Indicates the access is a write. PTBE[3:0]# D1. Indicates valid bytes for the first data transfer. Cloc k 2: Add-On logic sam p les PTAT N# an d PTBURST# asserted, indicating the start of a burst. The Add-On asserts PTADR# to read the Pass-Thru Address Register. As it is not ready to receive any data yet, it does not initiate a data read. Clock 3: Add-on logic latches the address. RD#, BE[3:0]#, ADR[6:2], and SELECT# inputs are asserted to select the Pass-Thru Data Register during the next clock. PTRDY# is also asserted to indicate the com- pletion of the first data phase. Clock 4: As the S5920 sampled PTRDY# asserted, the first data phase is completed DATA1 is driven on the DQ bus, a result of the read from the previous clock cycle. The PTBE# outputs are updated to indi- cate which bytes are valid for the second transfer. Add-on logic is not fast enough to store the next data, so a wait state is activated by deasserting PTRDY#. RD# is also deasserted. Clock 5: Add-On logic uses the rising edge of this clock to store DATA1. PTRDY# is sampled deas- serted, so a wait state is activated. PTRDY# is asserted to indicate that the Add-On is ready to accept the next data transfer. RD# is also asserted, request- ing DATA2 to be driven during the next clock cycle. Clock 6: PTRDY# is sampled asserted, thus complet- ing the current data-phase. DATA2 is driven on the DQ bus, a result of a read during the previous clock cycle. The PTBE# outputs are updated to indicate which bytes are valid for the third transfer. Add-on logic is not fast enough to store the next data, so a wait state is activated by deasserting PTRDY#. RD# is also deasserted. Clock 7: Add-On logic uses the rising edge of this clock to store DATA2. PTRDY# is sampled deas- serted, so a wait state is activated. PTRDY# is asserted to indicate that the Add-On is ready to accept the next data transfer. RD# is also asserted, request- ing DATA3 to be driven during the next clock cycle. Clock 8: PTRDY# is sampled asserted, thus complet- ing the current data-phase. DATA3 is driven on the DQ bus, a result of a read during the previous cycle. The PTBE# outputs are updated to indicate which bytes are valid for the fourth transfer. Add-On logic is not fast enough to store the next data, so a wait state is acti- vated by deasserting P T RDY#. RD# is also deasserted. Clock 9: Add-On logic uses the rising edge of this clock to store DATA3. PTRDY# is sampled deas- serted, so a wait state is activated. PTRDY# is asserted to indicate that the Add-On is ready to accept the next data transfer. RD# is also asserted, request- ing DATA4 to be driven during the next clock cycle. Clock 10: PTRDY# is sampled asserted, thus com- pleting the current data-phase. PTBURST# is deasserted, indicating that only one DWORD is left for transfer. DATA4 is driven on the Add-On DQ bus, a result of a read during the previous clock cycle. The PTBE# outputs are updated to indicate which bytes are valid for the last transfer. Add-On logic is not fast enough to store the next data, so a wait state is acti- vated by deasserting P T RDY#. RD# is also deasserted. Clock 11: Add-On logic uses the rising edge of this clock to store DATA4. PTRDY# is sampled deas- serted, so a wait state is activated. PTRDY# is asserted to indicate that the add-on is ready to accept the last data transfer. The add-on knows this is the last transfer as it has sampled PTBURST# deasserted and PTATN# asserted. RD# is also asserted, requesting DATA5 to be driven during the next clock cycle. Clock 12: PTRDY# is sampled asserted, indicating that the last transfer was completed. As a result, PTATN# is deasserted. As the Add-On has also fin- ished its transfer, it deasserts RD#, SELECT#, BE[3:0]#. The last data, DATA5, is driven on the Add- On DQ bus. Clock 13: Add-On logic uses the rising edge of this clock to store DATA5. As PTATN# is deasserted, the Pass-Thru access is complete, and the S5920 can accept new Pass-Thru accesses starting on the next clock. The other Pass-Thru signals can also change state (in anticipation of a new transfer). Pass-Thru Burst Reads A Pass-Thru burst read operation occurs when a PCI initiator reads multiple DWORDs from a Pass-Thru region. A burst transfer consists of a single address and multiple data phases. The S5920 stores the PCI |
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