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DP83255AVF 数据表(PDF) 3 Page - National Semiconductor (TI) |
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DP83255AVF 数据表(HTML) 3 Page - National Semiconductor (TI) |
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3 / 96 page  10 FDDI Chip Set Overview National Semiconductor’s FDDI chip set consists of five components as shown in Figure 1-1 For more information on the other devices of the chip set consult the appropriate datasheets and application notes DP83231 CRDTM Device Clock Recovery Device The Clock Recovery Device extracts a 125 MHz clock from the incoming bit stream Features PHY Layer loopback test Crystal controlled Clock locks in less than 85 ms DP83241 CDDTM Device Clock Distribution Device From a 125 MHz reference the Clock Distribution Device synthesizes the 125 MHz 25 MHz and 125 MHz clocks required by the BSI BMAC and PLAYER devices DP8325155 PLAYERTM Device Physical Layer Controller The PLAYER device implements the Physical Layer (PHY) protocol as defined by the ANSI FDDI PHY X3T95 Stan- dard Features 4B5B encoders and decoders Framing logic Elasticity Buffer Repeat Filter and Smoother Line state detectorgenerator Link error detector Configuration switch Full duplex operation Separate management port that is used to configure and control their operation In addition the DP83255 contains an additional PHY Datarequest and PHY Dataindicate port required for concentrators and dual attach stations DP83261 BMACTM Device Media Access Controller The BMAC device implements the Timed Token Media Ac- cess Control protocol defined by the ANSI FDDI X3T95 MAC Standard Features All of the standard defined ring service options Full duplex operation with through parity Supports all FDDI Ring Scheduling Classes (Synchro- nous Asynchronous etc) Supports Individual Group Short Long and External Addressing Generates Beacon Claim and Void frames internally Extensive ring and station statistic gathering Extensions for MAC level bridging Separate management port that is used to configure and control their operation Multi-frame streaming interface DP83265 BSITM Device System Interface The BSI device implements the interface between the BMAC device and a host system Features 32-bit wide AddressData path with byte parity Programmable transfer burst sizes of 4 or 8 32-bit words Interfaces to low cost DRAMs or directly to system bus Provides 2 Output and 3 Input Channels Supports HeaderInfo splitting Efficient data structures Programmable Big or Little Endian alignment Full duplex data path allows transmission to self Confirmation status batching services Receive frame filtering services Operates from 125 MHz to 25 MHz synchronously with the host system 3 |
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