DP83255AVF datasheet(35/96 Pages) NSC

35 / 96 page

50 Registers (Continued)

RECEIVE CONDITION REGISTER B (RCRB)

The Receive Condition Register B maintains a historical record of the Line States recognized by the Receiver Block

When a new Line State is entered the bit corresponding to that line state is set to 1 The bits corresponding to the previous Line

States are not clear by the PLAYER device thereby maintaining a record of the Line States detected

The Receive Condition B bit (RCB) of the Interrupt Condition Register (ICR) will be set to 1 when one or more bits within the

Receive Condition Register B is set to 1 and the corresponding mask bits in Receive Condition Mask Register B (RCMRB) is

also set to 1

ACCESS RULES

ADDRESS

READ

WRITE

0Ah

Always

Conditional

RES

SILS

EBOU

CSE

LSUPV

ALS

ILS

Bit

Symbol

Description

ILS

IDLE LINE STATE

Received a minimum of two consecutive Idle symbol

pairs (11111 11111)

STATE THRESHOLD

This bit will be set to 1 by the PLAYER device when

the internal State Counter reaches zero It will remain set until a value equal

to or greater than one is loaded into the State Threshold Register or State

Prescale Threshold Register and this register is cleared

During the reset process (ie RST e GND) since the State Counter is

initialized to 0 the State Threshold bit is set to 1

ALS

ACTIVE LINE STATE

Received a JK symbol pair (11000 10001) and

possibly data symbols following

LSUPV

LINE STATE UNKNOWN

PHY VALID

Receiver Block has not detected

the minimum conditions to enter a know line state when the most recently

known line state was one of the following line states Active Line State or Idle

Line State

CSE

CASCADE SYNCHRONIZATION ERROR

When a synchronization error

occurs the Cascade Synchronization Error bit is set to 1

A synchronization error occurs if the Cascade Start signal (CS) is not asserted

within approximately 80 ns of Cascade Ready (CR) release

EBOU

ELASTICITY BUFFER UNDERFLOWOVERFLOW

The Elasticity Buffer

has either overflowed or underflowed The Elasticity Buffer will automatically

recover if the condition which caused the error is only transient

SILS

SUPER IDLE LINE STATE

Received a minimum of eight Idle symbol pairs

(11111 11111)

RES

RESERVED

Reserved for future use The reserved bit is set to 0 during the

reset process

Note

Users are discouraged from using this bit It may be set or cleared without any

effects to the functionality of the PLAYER device

DP83255AVF 数据表(PDF) 35 Page - National Semiconductor (TI)

DP83255AVF 数据表(HTML) 35 Page - National Semiconductor (TI)

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