DP83255AVF datasheet(7/96 Pages) NSC

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30 Functional Description (Continued)

No Signal Detect

The Line State Detector recognizes the incoming data to be

in the No Signal Detect state upon the deassertion of the

Signal Detect signal No Signal Detect indicates that the

incoming link is inactive

Master Line State

The Line State Detector recognizes the incoming data to be

in the Master Line State upon the reception of eight consec-

utive Halt-Quiet symbol pairs nominally (plus up to 2 symbol

pairs in start up cases)

The Master Line State is used in the handshake sequence

of the PHY Connection Management process

Halt Line State

The Line State Detector recognizes the incoming data to be

in the Halt Line State upon the reception of eight consecu-

tive Halt symbol pairs nominally (plus up to 2 symbol pairs in

start up cases)

The Halt Line State is used in the handshake sequence of

the PHY Connection Management process

Quiet Line State

The Line State Detector recognizes the incoming data to be

in the Quiet Line State upon the reception of eight consecu-

tive Quiet symbol pairs nominally (plus up to 9 bits of 0 in

start up cases)

The Quiet Line State is used in the handshake sequence of

the PHY Connection Management process

Noise Line State

The Line State Detector recognizes the incoming data to be

in the Noise Line State upon the reception of 16 noise sym-

bol pairs

The Noise Line State indicates that data is not received

correctly A detailed description of a noise event can be

found in Section 82

Line State Unknown

The Line State Detector recognizes the incoming data to be

in the Line State Unknown state upon the reception of one

inconsistent symbol pair (ie data that is not expected) This

may be the beginning of a new line state

Line State Unknown indicates that data is not received cor-

rectly If the condition persists the noise line state may be

entered

ELASTICITY BUFFER

The Elasticity Buffer performs the function of a ‘‘variable

depth’’ FIFO to compensate for clock skews between the

Receive Clock (RXCg) and the Local Byte Clock (LBC)

Bit 5 (EBOU) of the Receive Condition Register B (RCRB) is

set to 1 to indicate an error condition when the Elasticity

Buffer cannot compensate for the clock skews

The Elasticity Buffer will support maximum clock skews of

50 ppm with a maximum packet length of 4500 bytes

To make up for the accumulation of frequency disparity be-

tween the two clocks the Elasticity Buffer will insert or de-

lete Idle symbol pairs in the preamble Data is written into

the byte-wide registers of the Elasticity Buffer with the Re-

ceive Clock while data is read from the registers with the

Local Byte Clock

The Elasticity Buffer will recenter (ie set the read and write

pointers to a predetermined distance from each other) upon

the detection of a JK or every four byte times during PHY

Invalid (ie MLS HLS QLS NLS NSD) and Idle Line State

To resolve metastability problems the Elasticity Buffer is

designed such that a given register cannot be written and

read simultaneously under normal operating conditions In a

symbol-wide station a 5-bit off boundary JK following after a

maximum size frame situation may be produced which may

result in a small increase in the probability of an error

caused by a metastability condition

LINK ERROR DETECTOR

The Link Error Detector provides continuous monitoring of

an active link (ie during Active and Idle Line States) to

insure that it meets the minimum Bit Error Rate requirement

as set by the standard or user to remain on the ring

Upon detecting a link error the internal 8-bit Link Error Mon-

itor Counter is decremented The start value for the Link

Error Monitor Counter is programmed through the Link Error

Threshold Register (LETR) When the Link Error Monitor

Counter reaches zero bit 4 (LEMT) of the Interrupt Condi-

tion Register (ICR) is set to 1 The current value of the Link

Error Monitor Counter can be read through the Current Link

Error Count Register (CLECR) For higher error rates the

current value is an approximate count because the counter

rolls over

There are two ways to determine Link Error Rate polling

and interrupt

Polling

The Link Error Monitor Counter is set to the value of FF

This start value is programmed through the Link Error

Threshold Register (LETR)

Upon detecting a link error the Current Link Error Counter is

decremented

The Host System reads the current value of the Link Error

Monitor Counter via the Current Link Error Count Register

(CLECR) The Counter is then reset to FF

Interrupt

The Link Error Monitor Counter is set to the value of FF

This start value is programmed through the Link Error

Threshold Register (LETR)

Upon detecting a link error the Line Error Monitor Counter

is decremented When the counter reaches zero bit 4

(LEMT) of the Interrupt Condition Register (ICR) is set to 1

and the interrupt signal goes low

The Host System is interrupted when the Link Error Monitor

Counter reaches 0

A state table describing Link Errors in more detail can be

found in Section 83

Miscellaneous Items

When bit 0 (RUN) of the Mode Register (MR) is set to zero

or when the PLAYER device is reset through the Reset pin

(RST) the Signal Detect line (TTLSD) is internally forced to

zero and the Line State Detector is set to Line State Un-

known

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