DP83255AVF datasheet(5/96 Pages) NSC

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20 Architecture Description

(Continued)

PHY Port Interface

The PHY Port Interface connects the PLAYER device to

one or more BMAC devices andor PLAYER devices Each

PHY Port Interface consists of two byte-wide-interfaces

one for PHY Request data input to the PLAYER device and

one for the PHY Indicate data output of the PLAYER device

Each byte-wide interface consists of a parity bit (odd parity)

a control bit and two 4-bit symbols

The DP8355 PLAYER device has two PHY Port Interfaces

and the DP83251 has only one PHY Port Interface

Control Bus Interface

The Control Bus Interface connects the PLAYER device to

a wide variety of microprocessors and microcontrollers The

Control Bus is an asynchronous interface which provides

access to 32 8-bit registers

Clock Interface

The Clock Interface consists of 125 MHz and 125 MHz

clocks used by the PLAYER device

The clocks are generated by either the Clock Distribution

Device (CDD device) or the Clock Recovery Device (CRD

device)

Miscellaneous Interface

The Miscellaneous Interface consists of

A reset signal

User definable sense signals

User definable enable signals

Synchronization for cascaded PLAYER devices (a high-

performance non-FDDI mode)

CMOS power and ground and ECL ground and power

30 Functional Description

The PLAYER Device is comprised of four blocks Receiver

Transmitter Configuration Switch and Control Bus Inter-

face

31 RECEIVER BLOCK

During normal operation the Receiver Block accepts serial

data as inputs at the rate of 125 Mbps from the Clock Re-

covery Device (DP83231) During the Internal Loopback

mode of operation the Receiver Block accepts data from

the Transmitter Block as input

The Receiver Block performs the following operations

Converts the incoming data stream from NRZI to NRZ if

necessary

Decodes the data from 5B to 4B coding

Converts the serial bit stream into National byte-wide

code

Compensates for the differences between the upstream

and local clocks

Decodes Line States

Detects link errors

Finally the Receiver Block presents data symbol pairs to

the Configuration Switch Block

The Receiver Block consists of the following functional

blocks

NRZI to NRZ Decoder

Shift Register

Framing Logic

Symbol Decoder

Line State Detector

Elasticity Buffer

Link Error Detector

See

Figure 3-1

TLF10386 – 3

FIGURE 3-1 Receiver Block Diagram

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