DP83255AVF datasheet(73/96 Pages) NSC

73 / 96 page

60 Pin Descriptions (Continued)

CONTROL BUS INTERFACE

The Control Bus Interface consists of IO signals used to connect the PLAYER device to Station Management (SMT)

The Control Bus is an asynchronous interface between the PLAYER device and a general purpose microprocessor It provides

access to 32 8-bit internal registers

Refer to

Figure 22 Control Bus Timing Diagram for further information

Symbol

Pin No

Description

113

Chip Enable

An active-low TTL input signal which enables the Control Bus port for a

read or write cycle RW CBAk40l CBP and CBDk70l must be valid at the time CE

is low

112

Read EWrite

A TTL input signal which indicates a read Control Bus cycle (RW e 1)

or a write Control Bus cycle (RW e 0) This signal must be valid when CE is low and

held valid until ACK becomes low

ACK

123

Acknowledge

An active low TTL open drain output signal which indicates the

completion of a read or write cycle

During a read cycle CBDk70l are valid as long as ACK is low (ACK e 0)

During a write cycle a microprocessor must hold CBDk70l valid until ACK becomes

low

Once ACK is low it will remain low as long as CE remains low (CE e 0)

INT

114

Interrupt

An active low open drain TTL output signal indicating that an interrupt

condition has occurred The Interrupt Condition Register (ICR) should be read in order to

determine the source of the interrupt Interrupts can be masked through the use of the

Interrupt Condition Mask Register (ICMR)

CBA4

128

Control Bus Address

TTL input signals used to select the address of the register to be

read or written

CBA3

127

CBA2

126

CBA4 is the most significant bit and CBA0 is the least significant bit of the address

signals

CBA1

125

CBA0

124

These signals must be valid when CE is low and held valid until ACK becomes low

CBPE

Control Bus Parity Enable

A TTL input signal which during write cycles will enable or

disable the Control Bus parity checker Note that the Control Bus will always generate

parity during read cycles regardless of the state of this signal

CBP

Control Bus Parity

A bidirectional TTL signal representing odd parity for the Control

Bus data (CBDk70l)

During a read cycle the signal is held valid by the PLAYER device as long as ACK is low

During a write cycle the signal must be valid when CE is low and must be held valid until

ACK becomes low If incorrect parity is used during a write cycle the PLAYER device will

inhibit the write cycle and set the Control Bus Data Parity Error (CPE) bit in the Interrupt

Condition Register (ICR)

CBD7

Control Bus Data

Bidirectional TTL signals containing the data to be read from or

written to a register

CBD6

CBD5

During a read cycle the signal is held valid by the PLAYER device as long as ACK is low

CBD4

During a write cycle the signal must be valid when CE is low and must be held valid until

CBD3

ACK becomes low

CBD2

CBD1

131

CBD0

130

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