DP83255AVF datasheet(34/96 Pages) NSC

34 / 96 page

50 Registers (Continued)

RECEIVE CONDITION REGISTER A (RCRA)

The Receive Condition Register A maintains a historical record of the Line States recognized by the Receiver Block

When a new Line State is entered the bit corresponding to that line state is set to 1 The bits corresponding to the previous Line

States are not cleared by the PLAYER device thereby maintaining a record of the Line States detected

The Receive Condition A bit (RCA) of the Interrupt Condition Register (ICR) will be set to 1 when one or more bits within the

Receive Condition Register A is set to 1 and the corresponding mask bit(s) in Receive Condition Mask Register A (RCMRA) is

also set to 1

ACCESS RULES

ADDRESS

READ

WRITE

09h

Always

Conditional

LSUPI

LSC

NLS

MLS

HLS

QLS

NSD

Bit

Symbol

Description

NSD

NO SIGNAL DETECT

Indicates that the Signal Detect pin (TTLSD) has been

deasserted and that the Clock Recovery Device is not receiving data from the

Fiber Optic Receiver

QLS

QUIET LINE STATE

Received a minimum of eight consecutive Quiet symbol

pairs (00000 00000)

HLS

HALT LINE STATE

Received a minimum of eight consecutive Halt symbol

pairs (00100 00100)

MLS

MASTER LINE STATE

Received a minimum of eight consecutive Halt-Quiet

symbol pairs (00100 00000)

NLS

NOISE LINE STATE

Detected a minimum of sixteen noise events

NOISE THRESHOLD

This bit is set to 1 when the internal Noise Counter

reaches 0 It will remain set until a value equal to or greater than one is

loaded into the Noise Threshold Register or Noise Prescale Threshold

During the reset process (ie RST e GND) since the Noise Counter is

initialized to 0 the Noise Threshold bit will be set to 1

LSC

LINE STATE CHANGE

A line state change has been detected

LSUPI

LINE STATE UNKNOWN

PHY INVALID

The Receiver Block has not

detected the minimum conditions to enter a known line state

In addition the most recently known line state was one of the following line

states No Signal Detect Quiet Line State Halt Line State Master Line State

or Noise Line State

DP83255AVF 数据表(PDF) 34 Page - National Semiconductor (TI)

DP83255AVF 数据表(HTML) 34 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96

数据表下载