Preliminary Technical Data

AD5627R/AD5647R/AD5667R, AD5627/AD5667

Rev. PrA. | Page 9 of 30

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

GND

LDAC

CLR

SDA

SCL

ADDR

1

2

3

4

5

10

9

8

7

6

AD5627(R)

AD5647R

AD5667(R)

TOP VIEW

(Not to Scale)

Figure 3. Pin Configuration

Table 7. Pin Function Descriptions

Pin No.

(10-pin)

Mnemonic

Description

1

Analog output voltage from DAC C. The output amplifier has rail-to-rail operation.

2

Analog output voltage from DAC B. The output amplifier has rail-to-rail operation.

3

GND

Ground reference point for all circuitry on the part.

4

LDAC

Active low load DAC pin.

5

CLR

Asynchronous clear input. The

are ignored. When

output to 0 V. The part exits clear code mode on the 24th falling edge of the next write to the part. If

6

ADDR

Three-state address input. Sets the two least significant bits (Bit A1, Bit A0) of the 7-bit slave address.

7

SCL

Serial clock line. This is used in conjunction with the SDA line to clock data into or out of the 16-bit

input register.

8

SDA

Serial data line. This is used in conjunction with the SCL line to clock data into or out of the 16-bit

input register. It is a bidirectional, open-drain data line that should be pulled to the supply with an

external pull-up resistor.

9

Power supply input. These parts can be operated from 2.7 V to 5.5 V, and the supply should be

decoupled with a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND.

10

The AD5627R/AD5647R/AD5667R, AD5627/AD5667 have a common pin for reference input and

reference output. The internal reference and reference output are only available on suffix ---R

versions. When using the internal reference, this is the reference output pin. When using an external

reference, this is the reference input pin. The default for this pin is as a reference input.