AD5667-RBRMZ-2 datasheet(26/30 Pages) AD

26 / 30 page

AD5627R/AD5647R/AD5667R, AD5627/AD5667

Preliminary Technical Data

Rev. PrA. | Page 26 of 30

RESISTOR

NETWORK

VOUT

RESISTOR

STRING DAC

POWER-DOWN

CIRCUITRY

AMPLIFIER

Figure 62. Output Stage During Power-Down

The bias generator, the output amplifier, the resistor string, and

other associated linear circuitry are shutdown when power-

down mode is activated. However, the contents of the DAC

power-down is typically 4 µs for VDD = 5 V and for VDD = 3 V.

Figure 61 shows the format of the power up/down command.

Note that, during the power up/down command, the DAC

address bits A2 – A0 are ignored.

POWER-ON-RESET AND SOFTWARE RESET

The AD56x7 contains a power-on reset circuit that controls the

output voltage during power-up. The device powers up to 0V

and the output remains powered up at this level until a valid

write sequence is made to the DAC. This is useful in

applications where it is important to know the state of the

output of the DAC while it is in the process of powering up.

Any events on LDAC or CLR during power-on reset are

ignored.

There is also a software reset function. Command 101 is the

software reset command. The software reset command contains

two reset modes that are software programmable by setting bit

DB0 in the input shift register.

Table 12 shows how the state of the bit corresponds to the

software reset modes of operation of the devices. Figure 64

shows the contents of the input shift register during the

software reset mode of operation.

Table 12. Software Reset Modes for the

AD5627R/AD5647R/AD5667R, AD5627/AD5667

DB0

Registers reset to zero

DAC register

Input shift register

1 (Power-On Reset)

DAC register

Input shift register

LDAC register

Power-down register

Internal reference setup register

CLEAR PIN (CLR)

The AD56x7 has an asynchronous clear input. The CLR input is

falling edge sensitive.

While CLR is low, all LDAC pulses are

ignored. When CLR is activated, zero scale is loaded to all input

and DAC registers. This clears the output to 0 V. The part exits

clear code mode on the 24th falling edge of the next write to the

part. If CLR is activated during a write sequence, the write is

aborted. If CLR is activated during high speed mode the part

will exit high speed mode to fast mode.

COMMAND

DAC ADDRESS

(DON’T CARE)

DON’T CARE

DB15 DB14 DB13 DB12 DB11 DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB2

DB3

DB1

DB0

DON’T CARE

RST

RESET

MODE

RES

DON’T

CARE

Figure 63. Reset Command

INTERNAL REFERENCE SETUP (-R VERSIONS)

The on-chip reference is off at power-up by default. It can be

turned on by sending the reference setup command (111) and

setting DB0 in the input shift register. Table 14 shows how the

state of the bit corresponds to the mode of operation.

Table 14. Reference Setup Command

(DB0)

Action

Internal reference off (default)

Internal reference on

XXX

COMMAND

DAC ADDRESS

(DON’T CARE)

DON’T CARE

DB15 DB14 DB13 DB12 DB11 DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB2

DB3

DB1

DB0

DON’T CARE

REF

REF.

MODE

DON’T

CARE

RES

Figure 64. Reference Setup Command

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